On Fri, Mar 16, 2018 at 3:02 PM, Icenowy Zheng [off-list ref] wrote:

The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.

Change the current code that uses IRQ bank base to a IRQ bank map, in
order to support the case that holes exist among IRQ banks.

Signed-off-by: Icenowy Zheng <redacted>
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Extracted in v4.

Patch applied with Maxime's ACK.

Yours,
Linus Walleij