On Fri, Mar 9, 2018 at 7:13 AM, Manivannan Sadhasivam
[off-list ref] wrote:

Add gpio driver for Actions Semi OWL family S900 SoC. Set of registers
controlling the gpio shares the same register range with pinctrl block.

GPIO registers are organized as 6 banks and each bank controls the
maximum of 32 gpios.

+static void owl_gpio_set_reg(void __iomem *base, unsigned int pin, int flag)
+{
+       u32 val;
+
+       val = readl_relaxed(base);
+
+       if (flag)
+               val |= BIT(pin);
+       else
+               val &= ~BIT(pin);
+
+       writel_relaxed(val, base);
+}

The name is confusing. It's not exclusively set, it's an update.

+static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
+{
+       struct owl_gpio *gpio = gpiochip_get_data(chip);
+       u32 val;
+
+       val = readl_relaxed(gpio->base + GPIO_DAT);
+
+       if (value)
+               val |= BIT(offset);
+       else
+               val &= ~BIT(offset);
+
+       writel_relaxed(val, gpio->base + GPIO_DAT);

Forgot to replace?

+}

-- 
With Best Regards,
Andy Shevchenko