Re: [PATCH v5 0/5] Add OV5640 parallel interface and RGB565/YUYV support

Hi Maxime,

On Thu, 11 Jan 2018 13:40:18 +0100
Maxime Ripard [off-list ref] wrote:

Hi Yong,

On Thu, Jan 11, 2018 at 09:15:08AM +0800, Yong wrote:

quoted

quoted

On Mon, Jan 08, 2018 at 05:13:39PM +0000, Hugues FRUCHET wrote:

quoted

I'm using a ST board with OV5640 wired in parallel bus output in order 
to interface to my STM32 DCMI parallel interface.
Perhaps could you describe your setup so I could help on understanding 
the problem on your side. From my past experience with this sensor 
module, you can first check hsync/vsync polarities, the datasheet is 
buggy on VSYNC polarity as documented in patch 4/5.

It turns out that it was indeed a polarity issue.

It looks like that in order to operate properly, I need to setup the
opposite polarity on HSYNC and VSYNC on the interface. I looked at the
signals under a scope, and VSYNC is obviously inversed as you
described. HSYNC, I'm not so sure since the HBLANK period seems very
long, almost a line.

Since VSYNC at least looks correct, I'd be inclined to think that the
polarity is inversed on at least the SoC I'm using it on.

Yong, did you test the V3S CSI driver with a parallel interface? With
what sensor driver? Have you found some polarities issues like this?

Did you try it with Allwinner SoCs?

Yes, on an H3. Looking at all the Allwinner datasheet I could get my
hands on, they are all documented in the same way. However, I really
start to wonder whether the polarity shouldn't be reversed.

At least the fact that VSYNC is clearly active low on the
oscilloscope, while I have to set it active high in the controller
seems like a strong hint :)

The BSP code of Allwinner also treat V4L2_MBUS_VSYNC_ACTIVE_HIGH as
they documented 'positive'.
Maybe there need some more tests to confirm if the datasheet and BSP
code are both wrong.

quoted

No. I only tested with a BT1120 signal generated by FPGA or ADV7611. HSYNC
and VSYNC are not used.

Ok, that's good to know :)

quoted

For V3s CSI driver, I will add the following to dt-bindings:
Endpoint node properties for CSI1
---------------------------------

- remote-endpoint      : (required) a phandle to the bus receiver's endpoint
                          node
- bus-width:           : (required) must be 8, 10, 12 or 16
- pclk-sample          : (optional) (default: sample on falling edge)
- hsync-active         : (only required for parallel)
- vsync-active         : (only required for parallel)

You could try diffrent hsync-active/vsync-active values here.

I did already, and the only combination that works is the one that is
the inversed polarity on HSYNC and VSYNC than what the sensor setup.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Thanks,
Yong
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