Thread (62 messages) 62 messages, 9 authors, 2017-12-19

Re: [PATCH v3 09/33] nds32: Cache and TLB routines

From: Greentime Hu <hidden>
Date: 2017-12-13 08:31:28
Also in: linux-arch, linux-serial, lkml, netdev

2017-12-13 16:19 GMT+08:00 Guo Ren [off-list ref]:
On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote:
quoted
I think it should be fine if an interruption between mtsr_dsb and
tlbop_rwr because this is a optimization by sw.
Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will
break that vaddr's pfn in the CPU tlb-buffer entry. When linux access the
vaddr, it will get wrong data unless the entry has been replaced out.
Hi, Guo Ren:

Thanks. I get your point.
It is needed to be protected.
I will fix it in the next version patch.

if (vma->vm_mm == current->active_mm) {
        local_irq_save(flags);
        __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
        __nds32__tlbop_rwr(*pte);
        __nds32__isb();
        local_irq_restore(flags);
}
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