On Thu, Nov 30, 2017 at 6:48 AM, Greentime Hu [off-list ref] wrote:

2017-11-30 4:27 GMT+08:00 Arnd Bergmann [off-list ref]:

quoted

On Wed, Nov 29, 2017 at 3:10 PM, Greentime Hu [off-list ref] wrote:

quoted

2017-11-29 19:57 GMT+08:00 Arnd Bergmann [off-list ref]:

quoted

On Wed, Nov 29, 2017 at 12:39 PM, Greentime Hu [off-list ref] wrote:

I think I can use this name "CPU_V3" for all nds32 v3 compatible cpu.
It will be implemented like this.

config HWZOL
        bool "hardware zero overhead loop support"
        depends on CPU_D10 || CPU_D15
        default n
        help
          A set of Zero-Overhead Loop mechanism is provided to reduce the
          instruction fetch and execution overhead of loop-control instructions.
          It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
          You don't need to save these registers if you can make sure your user
          program doesn't use these registers.

          If unsure, say N.

config CPU_CACHE_NONALIASING
        bool "Non-aliasing cache"
        depends on !CPU_N10 && !CPU_D10
        default n
        help
          If this CPU is using VIPT data cache and its cache way size is larger
          than page size, say N. If it is using PIPT data cache, say Y.

          If unsure, say N.

I still think it will be easier to revert the logic, and have
CPU_CACHE_ALIASING.

Gr{oetje,eeting}s,

                        Geert