[PATCH 3/4] clk: renesas: cpg-mssr: Add du1 clock to R8A7745
From: Fabrizio Castro <hidden>
Date: 2017-10-13 15:22:21
Also in:
dri-devel, linux-clk, linux-renesas-soc
Subsystem:
common clk framework, renesas clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Geert Uytterhoeven, Linus Torvalds
Signed-off-by: Fabrizio Castro <redacted> Reviewed-by: Biju Das <redacted> --- drivers/clk/renesas/r8a7745-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 9e2360a..2859504 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c@@ -129,6 +129,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = { DEF_MOD("scif2", 719, R8A7745_CLK_P), DEF_MOD("scif1", 720, R8A7745_CLK_P), DEF_MOD("scif0", 721, R8A7745_CLK_P), + DEF_MOD("du1", 723, R8A7745_CLK_ZX), DEF_MOD("du0", 724, R8A7745_CLK_ZX), DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX), DEF_MOD("vin1", 810, R8A7745_CLK_ZG),
--
2.7.4