On 07/06/17 23:24, Rob Herring wrote:
On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
quoted
This commit adds the Device Tree binding documentation for the Marvell
GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
using memory transactions. It is used by the ICU unit in the Marvell
CP110 block to turn wired interrupts inside the CP into SPI interrupts
at the GIC level in the AP.
Sounds like an MSI block?
Almost. It also allows to deal with level interrupts, which a classic
MSI controller cannot manage. This looks like it has been lifted from
the GICv3 spec, which offers the exact same mechanism for SPIs.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html