Thread (1 message) 1 message, 1 author, 2017-05-16

Re: [PATCH 2/5] pintrl: meson: document GPIO IRQ DT binding

From: Rob Herring <hidden>
Date: 2017-05-16 00:31:26
Also in: linux-amlogic, linux-gpio

On Fri, May 12, 2017 at 4:41 PM, Heiner Kallweit [off-list ref] wrote:
Am 12.05.2017 um 21:38 schrieb Rob Herring:
quoted
On Sun, May 07, 2017 at 06:34:09PM +0200, Heiner Kallweit wrote:
quoted
Document the DT binding for GPIO IRQ support on Amlogic Meson SoC's.

This documentation is intentionally not placed under
interrupt-controllers as GPIO IRQ support on these SoC's acts more
like an interrupt multiplexer.

Signed-off-by: Heiner Kallweit <redacted>
---
 .../bindings/gpio/amlogic,meson-gpio-interrupt.txt | 30 ++++++++++++++++++++++
Seems more like an irqchip?
It is an irq_chip. Would you therefore prefer a different name or another location
for this binding documentation?
bindings/interrupt-controller
quoted
quoted
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/amlogic,meson-gpio-interrupt.txt
diff --git a/Documentation/devicetree/bindings/gpio/amlogic,meson-gpio-interrupt.txt b/Documentation/devicetree/bindings/gpio/amlogic,meson-gpio-interrupt.txt
new file mode 100644
index 00000000..35a052b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/amlogic,meson-gpio-interrupt.txt
@@ -0,0 +1,30 @@
+Amlogic meson GPIO interrupt controller
+
+Meson SoCs contains an interrupt controller which is able watch the SoC pads
+and generate an interrupt on edges or level. The controller is essentially a
+256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
+or level and polarity. We don't expose all 256 mux inputs because the
+documentation shows that upper part is not mapped to any pad. The actual number
+of interrupt exposed depends on the SoC.
+
+Required properties:
+
+- compatible : should be "amlogic,meson-gpio-interrupt", "syscon".
Why syscon?
Has been removed already in v2 of the patch.
quoted
quoted
+- reg : Specifies base physical address and size of the registers.
+- interrupts : list of GIC interrupts which can be used with the
+           GPIO IRQ multiplexer
What about interrupt-controller property?
This HW is somewhat special, it's more or less a multiplexer between
100+ GPIO's and 8 GIC IRQ's. And we have two GPIO domains, both having
a "gpio-controller".
It doesn't seem that the "interrupt-controller" property is right here.
I'd tend to say it should be added to the "gpio-controller" nodes.
I would say an interrupt controller is anything that controls
routing/delivery of interrupts from source to cpu. This certainly
meets that criteria.

You could even use interrupt-map property to statically assign the
sources to parent interrupts.

Rob
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