Geert Uytterhoeven [off-list ref] writes:

On Tue, May 23, 2017 at 11:45 PM, Babu Moger [off-list ref] wrote:

quoted

Found this problem while enabling queued rwlock on SPARC.
The parameter CONFIG_CPU_BIG_ENDIAN is used to clear the
specific byte in qrwlock structure. Without this parameter,
we clear the wrong byte. Here is the code.

static inline u8 *__qrwlock_write_byte(struct qrwlock *lock)
 {
        return (u8 *)lock + 3 * IS_BUILTIN(CONFIG_CPU_BIG_ENDIAN);
 }

Define CPU_BIG_ENDIAN for SPARC to fix it.

quoted

--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig

@@ -92,6 +92,10 @@ config ARCH_DEFCONFIG
 config ARCH_PROC_KCORE_TEXT
        def_bool y

+config CPU_BIG_ENDIAN
+       bool
+       default y if SPARC

Nice catch!

Traditionally, CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN were defined only on
architectures that may support both.  And it was checked in platform code
and drivers only.
Hence the symbol is lacking from most architectures. Heck, even
architectures that support both may default to one endiannes, and declare
only the symbol for the other endianness:

I guess there's a reason we can't use __BIG_ENDIAN__ / __LITTLE_ENDIAN__ ?

cheers
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