On Sat, May 6, 2017 at 12:07 AM, Bjorn Andersson
[off-list ref] wrote:

On Fri 05 May 03:26 PDT 2017, Jassi Brar wrote:

quoted

On Fri, May 5, 2017 at 1:35 AM, Bjorn Andersson
[off-list ref] wrote:

quoted

+
+static int qcom_apcs_ipc_send_data(struct mbox_chan *chan, void *data)
+{
+       struct qcom_apcs_ipc *apcs = container_of(chan->mbox,
+                                                 struct qcom_apcs_ipc, mbox);
+       unsigned long idx = (unsigned long)chan->con_priv;
+
+       writel(BIT(idx), apcs->base + apcs->offset);
+

When/how does this bit get ever cleared again?
You may want to add last_tx_done() callback to check if this bit is
cleared before you can send the next interrupt. And set
txdone_poll/irq accordingly.

It's a write-only register, writing a bit fires off an edge triggered
interrupt on the specific remote processor, which will ack the
associated IRQ status and handle the interrupt.

As the "message" is just a notification to the other side that it needs
to act on "something", there's no harm in notifying it multiple times
before it has a chance to ack the IRQ and a write after that will be
seen as a separate interrupt.

What causes it to return to '0'?

I think the driver should wait for it to become 0 before writing 1.
For example, the protocol has a command that says to remote cpu to
increase the voltage supply by 0.1v. This command is filled in a
structure and laid out in the shared memory before you ring the
'doorbell'.  In this situation you don't want the remote cpu to act
twice on the same command. Also for a new command, you don't want to
overwrite the last command packet before remote cpu has consumed it.
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