On 02/03, Chris Packham wrote:

The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.

Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
 .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
 drivers/clk/mvebu/Makefile                         |   2 +-
 drivers/clk/mvebu/armada-xp.c                      |  13 --
 drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++

This mixes dts and clk driver changes. Any chance it can be split
up and just have the clk part go through clk tree? Otherwise, I
can ack this if you want to take it all through arm-soc?

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