Re: [PATCH v6 02/14] clk: qcom: Add rcg ops to return floor value closest to the requested rate

Hi Rajendra,

[auto build test WARNING on ulf.hansson-mmc/next]
[also build test WARNING on v4.9-rc4 next-20161028]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Ritesh-Harjani/mmc-sdhci-msm-Add-clk-rates-DDR-HS400-support/20161107-203031
base:   https://git.linaro.org/people/ulf.hansson/mmc next
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   drivers/clk/qcom/clk-rcg2.c: In function '_freq_tbl_determine_rate':

quoted

drivers/clk/qcom/clk-rcg2.c:192:2: warning: switch condition has boolean value [-Wswitch-bool]

     switch (match) {
     ^~~~~~
   drivers/clk/qcom/clk-rcg2.c: In function '__clk_rcg2_set_rate':
   drivers/clk/qcom/clk-rcg2.c:297:2: warning: switch condition has boolean value [-Wswitch-bool]
     switch (match) {
     ^~~~~~

coccinelle warnings: (new ones prefixed by >>)

quoted

drivers/clk/qcom/clk-rcg2.c:306:2-3: Unneeded semicolon

   drivers/clk/qcom/clk-rcg2.c:201:2-3: Unneeded semicolon

Please review and possibly fold the followup patch.

vim +192 drivers/clk/qcom/clk-rcg2.c

   186	{
   187		unsigned long clk_flags, rate = req->rate;
   188		struct clk_hw *p;
   189		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
   190		int index;
   191	
 > 192		switch (match) {
   193		case FLOOR:
   194			f = qcom_find_freq_floor(f, rate);
   195			break;
   196		case CEIL:
   197			f = qcom_find_freq(f, rate);
   198			break;
   199		default:
   200			return -EINVAL;
   201		};
   202	
   203		if (!f)
   204			return -EINVAL;
   205	
   206		index = qcom_find_src_index(hw, rcg->parent_map, f->src);
   207		if (index < 0)
   208			return index;
   209	
   210		clk_flags = clk_hw_get_flags(hw);
   211		p = clk_hw_get_parent_by_index(hw, index);
   212		if (clk_flags & CLK_SET_RATE_PARENT) {
   213			if (f->pre_div) {
   214				rate /= 2;
   215				rate *= f->pre_div + 1;
   216			}
   217	
   218			if (f->n) {
   219				u64 tmp = rate;
   220				tmp = tmp * f->n;
   221				do_div(tmp, f->m);
   222				rate = tmp;
   223			}
   224		} else {
   225			rate =  clk_hw_get_rate(p);
   226		}
   227		req->best_parent_hw = p;
   228		req->best_parent_rate = rate;
   229		req->rate = f->freq;
   230	
   231		return 0;
   232	}
   233	
   234	static int clk_rcg2_determine_rate(struct clk_hw *hw,
   235					   struct clk_rate_request *req)
   236	{
   237		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
   238	
   239		return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
   240	}
   241	
   242	static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
   243						 struct clk_rate_request *req)
   244	{
   245		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
   246	
   247		return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
   248	}
   249	
   250	static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
   251	{
   252		u32 cfg, mask;
   253		struct clk_hw *hw = &rcg->clkr.hw;
   254		int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
   255	
   256		if (index < 0)
   257			return index;
   258	
   259		if (rcg->mnd_width && f->n) {
   260			mask = BIT(rcg->mnd_width) - 1;
   261			ret = regmap_update_bits(rcg->clkr.regmap,
   262					rcg->cmd_rcgr + M_REG, mask, f->m);
   263			if (ret)
   264				return ret;
   265	
   266			ret = regmap_update_bits(rcg->clkr.regmap,
   267					rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
   268			if (ret)
   269				return ret;
   270	
   271			ret = regmap_update_bits(rcg->clkr.regmap,
   272					rcg->cmd_rcgr + D_REG, mask, ~f->n);
   273			if (ret)
   274				return ret;
   275		}
   276	
   277		mask = BIT(rcg->hid_width) - 1;
   278		mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
   279		cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
   280		cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
   281		if (rcg->mnd_width && f->n && (f->m != f->n))
   282			cfg |= CFG_MODE_DUAL_EDGE;
   283		ret = regmap_update_bits(rcg->clkr.regmap,
   284				rcg->cmd_rcgr + CFG_REG, mask, cfg);
   285		if (ret)
   286			return ret;
   287	
   288		return update_config(rcg);
   289	}
   290	
   291	static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
   292				       bool match)
   293	{
   294		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
   295		const struct freq_tbl *f;
   296	
   297		switch (match) {
   298		case FLOOR:
   299			f = qcom_find_freq_floor(rcg->freq_tbl, rate);
   300			break;
   301		case CEIL:
   302			f = qcom_find_freq(rcg->freq_tbl, rate);
   303			break;
   304		default:
   305			return -EINVAL;
 > 306		};
   307	
   308		if (!f)
   309			return -EINVAL;

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