[PATCH 0/3] sx150x update - bugfix, cleanup, last 4 chips

STALE3580d

9 messages, 3 authors, 2016-11-25 · open the first message on its own page

[PATCH 0/3] sx150x update - bugfix, cleanup, last 4 chips

From: Peter Rosin <hidden>
Date: 2016-11-24 21:19:01

Hi!

Yet another sx150x update, only the first is critical.

Cheers,
Peter

Peter Rosin (3):
  pinctrl: sx150x: use correct registers for reg_sense (sx1502 and
    sx1508)
  pinctrl: sx150x: sort chips by part number
  pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507

 .../devicetree/bindings/pinctrl/pinctrl-sx150x.txt |  14 +-
 drivers/pinctrl/pinctrl-sx150x.c                   | 206 +++++++++++++++------
 2 files changed, 161 insertions(+), 59 deletions(-)

-- 
2.1.4

[PATCH 3/3] pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507

From: Peter Rosin <hidden>
Date: 2016-11-24 20:46:22

Untested, register offsets carefully copied from datasheets.

Signed-off-by: Peter Rosin <redacted>
---
 .../devicetree/bindings/pinctrl/pinctrl-sx150x.txt |  8 +-
 drivers/pinctrl/pinctrl-sx150x.c                   | 98 ++++++++++++++++++++++
 2 files changed, 104 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
index 83f8d5c449ba..bf76867168e9 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt

@@ -6,9 +6,13 @@ pin controller, GPIO, and interrupt bindings.
 
 Required properties:
 - compatible: should be one of :
+			"semtech,sx1501q",
 			"semtech,sx1502q",
 			"semtech,sx1503q",
+			"semtech,sx1504q",
+			"semtech,sx1505q",
 			"semtech,sx1506q",
+			"semtech,sx1507q",
 			"semtech,sx1508q",
 			"semtech,sx1509q".

@@ -28,7 +32,7 @@ Optional properties :
 - interrupt-controller: Marks the device as a interrupt controller.
 
 - semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
-		only for sx1508q and sx1509q
+		only for sx1507q, sx1508q and sx1509q
 
 The GPIO expander can optionally be used as an interrupt controller, in
 which case it uses the default two cell specifier.

@@ -43,7 +47,7 @@ Optional properties for pin configuration sub-nodes:
  - bias-pull-down: pull down the pin, except the OSCIO pin
  - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin
  - drive-push-pull: drive actively high and low
- - drive-open-drain: drive with open drain only for sx1508q and sx1509q and except the OSCIO pin
+ - drive-open-drain: drive with open drain only for sx1507q, sx1508q and sx1509q and except the OSCIO pin
  - output-low: set the pin to output mode with low level
  - output-high: set the pin to output mode with high level

diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index 97df9302e84b..eb6adbbd33f0 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c

@@ -116,6 +116,14 @@ struct sx150x_pinctrl {
 	const struct sx150x_device_data *data;
 };
 
+static const struct pinctrl_pin_desc sx150x_4_pins[] = {
+	PINCTRL_PIN(0, "gpio0"),
+	PINCTRL_PIN(1, "gpio1"),
+	PINCTRL_PIN(2, "gpio2"),
+	PINCTRL_PIN(3, "gpio3"),
+	PINCTRL_PIN(8, "oscio"),
+};
+
 static const struct pinctrl_pin_desc sx150x_8_pins[] = {
 	PINCTRL_PIN(0, "gpio0"),
 	PINCTRL_PIN(1, "gpio1"),

@@ -148,6 +156,26 @@ static const struct pinctrl_pin_desc sx150x_16_pins[] = {
 	PINCTRL_PIN(16, "oscio"),
 };
 
+static const struct sx150x_device_data sx1501q_device_data = {
+	.model = SX150X_123,
+	.reg_pullup	= 0x02,
+	.reg_pulldn	= 0x03,
+	.reg_dir	= 0x01,
+	.reg_data	= 0x00,
+	.reg_irq_mask	= 0x05,
+	.reg_irq_src	= 0x08,
+	.reg_sense	= 0x07,
+	.pri.x123 = {
+		.reg_pld_mode	= 0x10,
+		.reg_pld_table0	= 0x11,
+		.reg_pld_table2	= 0x13,
+		.reg_advance	= 0xad,
+	},
+	.ngpios	= 4,
+	.pins = sx150x_4_pins,
+	.npins = 4, /* oscio not available */
+};
+
 static const struct sx150x_device_data sx1502q_device_data = {
 	.model = SX150X_123,
 	.reg_pullup	= 0x02,

@@ -194,6 +222,47 @@ static const struct sx150x_device_data sx1503q_device_data = {
 	.npins  = 16, /* oscio not available */
 };
 
+static const struct sx150x_device_data sx1504q_device_data = {
+	.model = SX150X_456,
+	.reg_pullup	= 0x02,
+	.reg_pulldn	= 0x03,
+	.reg_dir	= 0x01,
+	.reg_data	= 0x00,
+	.reg_irq_mask	= 0x05,
+	.reg_irq_src	= 0x08,
+	.reg_sense	= 0x07,
+	.pri.x456 = {
+		.reg_pld_mode	= 0x10,
+		.reg_pld_table0	= 0x11,
+		.reg_pld_table2	= 0x13,
+	},
+	.ngpios	= 4,
+	.pins = sx150x_4_pins,
+	.npins = 4, /* oscio not available */
+};
+
+static const struct sx150x_device_data sx1505q_device_data = {
+	.model = SX150X_456,
+	.reg_pullup	= 0x02,
+	.reg_pulldn	= 0x03,
+	.reg_dir	= 0x01,
+	.reg_data	= 0x00,
+	.reg_irq_mask	= 0x05,
+	.reg_irq_src	= 0x08,
+	.reg_sense	= 0x06,
+	.pri.x456 = {
+		.reg_pld_mode	= 0x10,
+		.reg_pld_table0	= 0x11,
+		.reg_pld_table1	= 0x12,
+		.reg_pld_table2	= 0x13,
+		.reg_pld_table3	= 0x14,
+		.reg_pld_table4	= 0x15,
+	},
+	.ngpios	= 8,
+	.pins = sx150x_8_pins,
+	.npins = 8, /* oscio not available */
+};
+
 static const struct sx150x_device_data sx1506q_device_data = {
 	.model = SX150X_456,
 	.reg_pullup	= 0x04,

@@ -217,6 +286,27 @@ static const struct sx150x_device_data sx1506q_device_data = {
 	.npins = 16, /* oscio not available */
 };
 
+static const struct sx150x_device_data sx1507q_device_data = {
+	.model = SX150X_789,
+	.reg_pullup	= 0x03,
+	.reg_pulldn	= 0x04,
+	.reg_dir	= 0x07,
+	.reg_data	= 0x08,
+	.reg_irq_mask	= 0x09,
+	.reg_irq_src	= 0x0b,
+	.reg_sense	= 0x0a,
+	.pri.x789 = {
+		.reg_drain	= 0x05,
+		.reg_polarity	= 0x06,
+		.reg_clock	= 0x0d,
+		.reg_misc	= 0x0e,
+		.reg_reset	= 0x7d,
+	},
+	.ngpios = 4,
+	.pins = sx150x_4_pins,
+	.npins = ARRAY_SIZE(sx150x_4_pins),
+};
+
 static const struct sx150x_device_data sx1508q_device_data = {
 	.model = SX150X_789,
 	.reg_pullup	= 0x03,

@@ -758,18 +848,26 @@ static const struct pinconf_ops sx150x_pinconf_ops = {
 };
 
 static const struct i2c_device_id sx150x_id[] = {
+	{"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
 	{"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
 	{"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
+	{"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
+	{"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
 	{"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
+	{"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
 	{"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
 	{"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
 	{}
 };
 
 static const struct of_device_id sx150x_of_match[] = {
+	{ .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
 	{ .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
 	{ .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
+	{ .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
+	{ .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
 	{ .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
+	{ .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
 	{ .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
 	{ .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
 	{},

-- 
2.1.4

[PATCH 1/3] pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)

From: Peter Rosin <hidden>
Date: 2016-11-24 21:00:41

All other registers on these chips are 8-bit, but reg_sense is 16-bits
and therefore needs to be moved down one notch.
This was apparently overlooked in the conversion to regmap, which only
updated the register locations for the 16-bit chips.

Fixes: 6489677f86c3 ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API")
Signed-off-by: Peter Rosin <redacted>
---
 drivers/pinctrl/pinctrl-sx150x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index f9e559e22537..a19c814843aa 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c

@@ -156,7 +156,7 @@ static const struct sx150x_device_data sx1508q_device_data = {
 	.reg_data	= 0x08,
 	.reg_irq_mask	= 0x09,
 	.reg_irq_src	= 0x0c,
-	.reg_sense	= 0x0b,
+	.reg_sense	= 0x0a,
 	.pri.x789 = {
 		.reg_drain	= 0x05,
 		.reg_polarity	= 0x06,

@@ -221,7 +221,7 @@ static const struct sx150x_device_data sx1502q_device_data = {
 	.reg_data	= 0x00,
 	.reg_irq_mask	= 0x05,
 	.reg_irq_src	= 0x08,
-	.reg_sense	= 0x07,
+	.reg_sense	= 0x06,
 	.pri.x123 = {
 		.reg_pld_mode	= 0x10,
 		.reg_pld_table0	= 0x11,

-- 
2.1.4

Re: [PATCH 3/3] pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507

From: Peter Rosin <hidden>
Date: 2016-11-24 21:02:43

On 2016-11-24 21:45, Peter Rosin wrote:

quoted hunk

Untested, register offsets carefully copied from datasheets.

Signed-off-by: Peter Rosin <redacted>
---
 .../devicetree/bindings/pinctrl/pinctrl-sx150x.txt |  8 +-
 drivers/pinctrl/pinctrl-sx150x.c                   | 98 ++++++++++++++++++++++
 2 files changed, 104 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
index 83f8d5c449ba..bf76867168e9 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt

@@ -6,9 +6,13 @@ pin controller, GPIO, and interrupt bindings.
 
 Required properties:
 - compatible: should be one of :
+			"semtech,sx1501q",
 			"semtech,sx1502q",
 			"semtech,sx1503q",
+			"semtech,sx1504q",
+			"semtech,sx1505q",
 			"semtech,sx1506q",
+			"semtech,sx1507q",
 			"semtech,sx1508q",
 			"semtech,sx1509q".

@@ -28,7 +32,7 @@ Optional properties :
 - interrupt-controller: Marks the device as a interrupt controller.
 
 - semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
-		only for sx1508q and sx1509q
+		only for sx1507q, sx1508q and sx1509q
 
 The GPIO expander can optionally be used as an interrupt controller, in
 which case it uses the default two cell specifier.

@@ -43,7 +47,7 @@ Optional properties for pin configuration sub-nodes:
  - bias-pull-down: pull down the pin, except the OSCIO pin
  - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin
  - drive-push-pull: drive actively high and low
- - drive-open-drain: drive with open drain only for sx1508q and sx1509q and except the OSCIO pin
+ - drive-open-drain: drive with open drain only for sx1507q, sx1508q and sx1509q and except the OSCIO pin
  - output-low: set the pin to output mode with low level
  - output-high: set the pin to output mode with high level

diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index 97df9302e84b..eb6adbbd33f0 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c

@@ -116,6 +116,14 @@ struct sx150x_pinctrl {
 	const struct sx150x_device_data *data;
 };
 
+static const struct pinctrl_pin_desc sx150x_4_pins[] = {
+	PINCTRL_PIN(0, "gpio0"),
+	PINCTRL_PIN(1, "gpio1"),
+	PINCTRL_PIN(2, "gpio2"),
+	PINCTRL_PIN(3, "gpio3"),
+	PINCTRL_PIN(8, "oscio"),

Should of course be:
+	PINCTRL_PIN(4, "oscio"),

If you want an updated patch, just ask...

Cheers,
Peter

quoted hunk

+};
+
 static const struct pinctrl_pin_desc sx150x_8_pins[] = {
 	PINCTRL_PIN(0, "gpio0"),
 	PINCTRL_PIN(1, "gpio1"),

@@ -148,6 +156,26 @@ static const struct pinctrl_pin_desc sx150x_16_pins[] = {
 	PINCTRL_PIN(16, "oscio"),
 };
 
+static const struct sx150x_device_data sx1501q_device_data = {
+	.model = SX150X_123,
+	.reg_pullup	= 0x02,
+	.reg_pulldn	= 0x03,
+	.reg_dir	= 0x01,
+	.reg_data	= 0x00,
+	.reg_irq_mask	= 0x05,
+	.reg_irq_src	= 0x08,
+	.reg_sense	= 0x07,
+	.pri.x123 = {
+		.reg_pld_mode	= 0x10,
+		.reg_pld_table0	= 0x11,
+		.reg_pld_table2	= 0x13,
+		.reg_advance	= 0xad,
+	},
+	.ngpios	= 4,
+	.pins = sx150x_4_pins,
+	.npins = 4, /* oscio not available */
+};
+
 static const struct sx150x_device_data sx1502q_device_data = {
 	.model = SX150X_123,
 	.reg_pullup	= 0x02,
@@ -194,6 +222,47 @@ static const struct sx150x_device_data sx1503q_device_data = {
 	.npins  = 16, /* oscio not available */
 };
 
+static const struct sx150x_device_data sx1504q_device_data = {
+	.model = SX150X_456,
+	.reg_pullup	= 0x02,
+	.reg_pulldn	= 0x03,
+	.reg_dir	= 0x01,
+	.reg_data	= 0x00,
+	.reg_irq_mask	= 0x05,
+	.reg_irq_src	= 0x08,
+	.reg_sense	= 0x07,
+	.pri.x456 = {
+		.reg_pld_mode	= 0x10,
+		.reg_pld_table0	= 0x11,
+		.reg_pld_table2	= 0x13,
+	},
+	.ngpios	= 4,
+	.pins = sx150x_4_pins,
+	.npins = 4, /* oscio not available */
+};
+
+static const struct sx150x_device_data sx1505q_device_data = {
+	.model = SX150X_456,
+	.reg_pullup	= 0x02,
+	.reg_pulldn	= 0x03,
+	.reg_dir	= 0x01,
+	.reg_data	= 0x00,
+	.reg_irq_mask	= 0x05,
+	.reg_irq_src	= 0x08,
+	.reg_sense	= 0x06,
+	.pri.x456 = {
+		.reg_pld_mode	= 0x10,
+		.reg_pld_table0	= 0x11,
+		.reg_pld_table1	= 0x12,
+		.reg_pld_table2	= 0x13,
+		.reg_pld_table3	= 0x14,
+		.reg_pld_table4	= 0x15,
+	},
+	.ngpios	= 8,
+	.pins = sx150x_8_pins,
+	.npins = 8, /* oscio not available */
+};
+
 static const struct sx150x_device_data sx1506q_device_data = {
 	.model = SX150X_456,
 	.reg_pullup	= 0x04,
@@ -217,6 +286,27 @@ static const struct sx150x_device_data sx1506q_device_data = {
 	.npins = 16, /* oscio not available */
 };
 
+static const struct sx150x_device_data sx1507q_device_data = {
+	.model = SX150X_789,
+	.reg_pullup	= 0x03,
+	.reg_pulldn	= 0x04,
+	.reg_dir	= 0x07,
+	.reg_data	= 0x08,
+	.reg_irq_mask	= 0x09,
+	.reg_irq_src	= 0x0b,
+	.reg_sense	= 0x0a,
+	.pri.x789 = {
+		.reg_drain	= 0x05,
+		.reg_polarity	= 0x06,
+		.reg_clock	= 0x0d,
+		.reg_misc	= 0x0e,
+		.reg_reset	= 0x7d,
+	},
+	.ngpios = 4,
+	.pins = sx150x_4_pins,
+	.npins = ARRAY_SIZE(sx150x_4_pins),
+};
+
 static const struct sx150x_device_data sx1508q_device_data = {
 	.model = SX150X_789,
 	.reg_pullup	= 0x03,
@@ -758,18 +848,26 @@ static const struct pinconf_ops sx150x_pinconf_ops = {
 };
 
 static const struct i2c_device_id sx150x_id[] = {
+	{"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
 	{"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
 	{"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
+	{"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
+	{"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
 	{"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
+	{"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
 	{"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
 	{"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
 	{}
 };
 
 static const struct of_device_id sx150x_of_match[] = {
+	{ .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
 	{ .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
 	{ .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
+	{ .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
+	{ .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
 	{ .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
+	{ .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
 	{ .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
 	{ .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
 	{},

[PATCH 2/3] pinctrl: sx150x: sort chips by part number

From: Peter Rosin <hidden>
Date: 2016-11-24 23:22:04

Signed-off-by: Peter Rosin <redacted>
---
 .../devicetree/bindings/pinctrl/pinctrl-sx150x.txt |   6 +-
 drivers/pinctrl/pinctrl-sx150x.c                   | 142 ++++++++++-----------
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
index 25b4ec80c759..83f8d5c449ba 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt

@@ -6,11 +6,11 @@ pin controller, GPIO, and interrupt bindings.
 
 Required properties:
 - compatible: should be one of :
+			"semtech,sx1502q",
+			"semtech,sx1503q",
 			"semtech,sx1506q",
 			"semtech,sx1508q",
-			"semtech,sx1509q",
-			"semtech,sx1502q",
-			"semtech,sx1503q".
+			"semtech,sx1509q".
 
 - reg: The I2C slave address for this device.

diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index a19c814843aa..97df9302e84b 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c

@@ -148,71 +148,6 @@ static const struct pinctrl_pin_desc sx150x_16_pins[] = {
 	PINCTRL_PIN(16, "oscio"),
 };
 
-static const struct sx150x_device_data sx1508q_device_data = {
-	.model = SX150X_789,
-	.reg_pullup	= 0x03,
-	.reg_pulldn	= 0x04,
-	.reg_dir	= 0x07,
-	.reg_data	= 0x08,
-	.reg_irq_mask	= 0x09,
-	.reg_irq_src	= 0x0c,
-	.reg_sense	= 0x0a,
-	.pri.x789 = {
-		.reg_drain	= 0x05,
-		.reg_polarity	= 0x06,
-		.reg_clock	= 0x0f,
-		.reg_misc	= 0x10,
-		.reg_reset	= 0x7d,
-	},
-	.ngpios = 8,
-	.pins = sx150x_8_pins,
-	.npins = ARRAY_SIZE(sx150x_8_pins),
-};
-
-static const struct sx150x_device_data sx1509q_device_data = {
-	.model = SX150X_789,
-	.reg_pullup	= 0x06,
-	.reg_pulldn	= 0x08,
-	.reg_dir	= 0x0e,
-	.reg_data	= 0x10,
-	.reg_irq_mask	= 0x12,
-	.reg_irq_src	= 0x18,
-	.reg_sense	= 0x14,
-	.pri.x789 = {
-		.reg_drain	= 0x0a,
-		.reg_polarity	= 0x0c,
-		.reg_clock	= 0x1e,
-		.reg_misc	= 0x1f,
-		.reg_reset	= 0x7d,
-	},
-	.ngpios	= 16,
-	.pins = sx150x_16_pins,
-	.npins = ARRAY_SIZE(sx150x_16_pins),
-};
-
-static const struct sx150x_device_data sx1506q_device_data = {
-	.model = SX150X_456,
-	.reg_pullup	= 0x04,
-	.reg_pulldn	= 0x06,
-	.reg_dir	= 0x02,
-	.reg_data	= 0x00,
-	.reg_irq_mask	= 0x08,
-	.reg_irq_src	= 0x0e,
-	.reg_sense	= 0x0a,
-	.pri.x456 = {
-		.reg_pld_mode	= 0x20,
-		.reg_pld_table0	= 0x22,
-		.reg_pld_table1	= 0x24,
-		.reg_pld_table2	= 0x26,
-		.reg_pld_table3	= 0x28,
-		.reg_pld_table4	= 0x2a,
-		.reg_advance	= 0xad,
-	},
-	.ngpios	= 16,
-	.pins = sx150x_16_pins,
-	.npins = 16, /* oscio not available */
-};
-
 static const struct sx150x_device_data sx1502q_device_data = {
 	.model = SX150X_123,
 	.reg_pullup	= 0x02,

@@ -259,6 +194,71 @@ static const struct sx150x_device_data sx1503q_device_data = {
 	.npins  = 16, /* oscio not available */
 };
 
+static const struct sx150x_device_data sx1506q_device_data = {
+	.model = SX150X_456,
+	.reg_pullup	= 0x04,
+	.reg_pulldn	= 0x06,
+	.reg_dir	= 0x02,
+	.reg_data	= 0x00,
+	.reg_irq_mask	= 0x08,
+	.reg_irq_src	= 0x0e,
+	.reg_sense	= 0x0a,
+	.pri.x456 = {
+		.reg_pld_mode	= 0x20,
+		.reg_pld_table0	= 0x22,
+		.reg_pld_table1	= 0x24,
+		.reg_pld_table2	= 0x26,
+		.reg_pld_table3	= 0x28,
+		.reg_pld_table4	= 0x2a,
+		.reg_advance	= 0xad,
+	},
+	.ngpios	= 16,
+	.pins = sx150x_16_pins,
+	.npins = 16, /* oscio not available */
+};
+
+static const struct sx150x_device_data sx1508q_device_data = {
+	.model = SX150X_789,
+	.reg_pullup	= 0x03,
+	.reg_pulldn	= 0x04,
+	.reg_dir	= 0x07,
+	.reg_data	= 0x08,
+	.reg_irq_mask	= 0x09,
+	.reg_irq_src	= 0x0c,
+	.reg_sense	= 0x0a,
+	.pri.x789 = {
+		.reg_drain	= 0x05,
+		.reg_polarity	= 0x06,
+		.reg_clock	= 0x0f,
+		.reg_misc	= 0x10,
+		.reg_reset	= 0x7d,
+	},
+	.ngpios = 8,
+	.pins = sx150x_8_pins,
+	.npins = ARRAY_SIZE(sx150x_8_pins),
+};
+
+static const struct sx150x_device_data sx1509q_device_data = {
+	.model = SX150X_789,
+	.reg_pullup	= 0x06,
+	.reg_pulldn	= 0x08,
+	.reg_dir	= 0x0e,
+	.reg_data	= 0x10,
+	.reg_irq_mask	= 0x12,
+	.reg_irq_src	= 0x18,
+	.reg_sense	= 0x14,
+	.pri.x789 = {
+		.reg_drain	= 0x0a,
+		.reg_polarity	= 0x0c,
+		.reg_clock	= 0x1e,
+		.reg_misc	= 0x1f,
+		.reg_reset	= 0x7d,
+	},
+	.ngpios	= 16,
+	.pins = sx150x_16_pins,
+	.npins = ARRAY_SIZE(sx150x_16_pins),
+};
+
 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 {
 	return 0;

@@ -758,20 +758,20 @@ static const struct pinconf_ops sx150x_pinconf_ops = {
 };
 
 static const struct i2c_device_id sx150x_id[] = {
-	{"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
-	{"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
-	{"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
 	{"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
 	{"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
+	{"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
+	{"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
+	{"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
 	{}
 };
 
 static const struct of_device_id sx150x_of_match[] = {
-	{ .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
-	{ .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
-	{ .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
 	{ .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
 	{ .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
+	{ .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
+	{ .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
+	{ .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
 	{},
 };

-- 
2.1.4

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Re: [PATCH 1/3] pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)

From: Linus Walleij <hidden>
Date: 2016-11-25 13:40:43

On Thu, Nov 24, 2016 at 9:45 PM, Peter Rosin [off-list ref] wrote:

All other registers on these chips are 8-bit, but reg_sense is 16-bits
and therefore needs to be moved down one notch.
This was apparently overlooked in the conversion to regmap, which only
updated the register locations for the 16-bit chips.

Fixes: 6489677f86c3 ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API")
Signed-off-by: Peter Rosin <redacted>

Patch applied.

Yours,
Linus Walleij

Re: [PATCH 2/3] pinctrl: sx150x: sort chips by part number

From: Linus Walleij <hidden>
Date: 2016-11-25 13:42:40

On Thu, Nov 24, 2016 at 9:45 PM, Peter Rosin [off-list ref] wrote:

Signed-off-by: Peter Rosin <redacted>

Pretty, satisfies my OCD.

Patch applied.

Yours,
Linus Walleij

Re: [PATCH 3/3] pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507

From: Linus Walleij <hidden>
Date: 2016-11-25 13:45:28

On Thu, Nov 24, 2016 at 9:45 PM, Peter Rosin [off-list ref] wrote:

Untested, register offsets carefully copied from datasheets.

Signed-off-by: Peter Rosin <redacted>

Why not. Nice to support all of them.

Patch applied, fixing the typ you mentioned in the follow
up in the process.

Yours,
Linus Walleij
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Re: [PATCH 3/3] pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507

From: Neil Armstrong <hidden>
Date: 2016-11-25 15:25:10

On 11/25/2016 02:45 PM, Linus Walleij wrote:

On Thu, Nov 24, 2016 at 9:45 PM, Peter Rosin [off-list ref] wrote:

quoted

Untested, register offsets carefully copied from datasheets.

Signed-off-by: Peter Rosin <redacted>

Why not. Nice to support all of them.

Patch applied, fixing the typ you mentioned in the follow
up in the process.

Yours,
Linus Walleij

Thanks peter,

Semtech should definitely provide some samples to test these variants !
I had a very hard time to find a (cheap) breakout board for one of these chips...

But it's better than nothing to have them supported by the kernel even if some bug may appear.

Neil
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