On Tuesday 15 November 2016 09:24 AM, William Wu wrote:
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock gate more sensible and stable.
Tested on rk3366/rk3399 EVB board.
merged to phy -next.
Thanks
Kishon
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2: correct 480MHz output clock stable time
drivers/phy/phy-rockchip-inno-usb2.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)