The A31 and A31s SoCs feature a different PWM controller with 4
channels, all channels have dedicated control register.
Add device nodes for them.
Signed-off-by: Icenowy Zheng <redacted>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ce19604..97626ce 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -322,6 +322,38 @@
#size-cells = <0>;
};
+ pwm0: pwm@01c21400 {
+ compatible = "allwinner,sun6i-a31-pwm";
+ reg = <0x01c21400 0x4>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@01c21410 {
+ compatible = "allwinner,sun6i-a31-pwm";
+ reg = <0x01c21400 0x4>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@01c21420 {
+ compatible = "allwinner,sun6i-a31-pwm";
+ reg = <0x01c21400 0x4>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@01c21430 {
+ compatible = "allwinner,sun6i-a31-pwm";
+ reg = <0x01c21430 0x4>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
usb_otg: usb@01c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;--
2.10.1