Hi Stephen/Adrian,

Let me give a little background on this. We would need more suggestions 
and opinion on this. Sorry for the delay it took.


Background -
Below change adds clk-rates DT entry since sdhci-msm driver uses this 
clk-rates table to find the nearest *floor* value of clock (this clock 
request comes will come from core layer) supported by msm platform.

Currently we don't have an API from clock driver which we can use it 
here to find these values(supported by msm platforms) and call for 
clk_set_rate. Hence the custom DT entry to have a table.

Please let us know if there is an API to find the floor value of clock 
from clock driver. I tried clk_set_max_rate, but it is not giving 
expected output (at least for msm platforms).


Comment-
The request from Stephen was to check if we could utilize OppV2 
framework since it provides an API - dev_pm_opp_find_freq_floor.
Also to check if we could get it done from existing clock driver APIs.
Please correct me I am missing anything.


Concern and opinion?
1. What about if there are more clocks getting added to sdhci DT node?
I see the Oppv2 framework taking device pointer as 1st argument. In 
cases where we have more than 1 clocks per device, how will Oppv2 handle 
this?
2. Here the concern is that shifting to Oppv2 framework only for use of 
this 1 API does not seems very useful. In case if there exist a clock 
driver API to do this, we may not have anything to be populated in DT.


Opinion and suggestions please?
Is it ok to continue to use clk-rates DT entry here for this case?


Regards
Ritesh


On 9/12/2016 11:47 AM, Ritesh Harjani wrote:

Hi Stephen,


On 9/7/2016 9:44 PM, Stephen Boyd wrote:

quoted

On 08/30, Ritesh Harjani wrote:

quoted

On 8/26/2016 3:57 AM, Stephen Boyd wrote:

quoted

On 08/24, Ritesh Harjani wrote:

quoted

This adds support for sdhc-msm controllers to get supported
clk-rates from DT. sdhci-msm would need it's own set_clock
ops to be implemented. For this, supported clk-rates needs
to be populated in sdhci_msm_pltfm_data.

Signed-off-by: Ritesh Harjani <redacted>
---

Please include the DT binding review list in binding updates.

Sure, will do it.

quoted

quoted

quoted

quoted

.../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
drivers/mmc/host/sdhci-msm.c                       | 60
++++++++++++++++++++++
2 files changed, 61 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt

b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 485483a..6a83b38 100644

--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt

@@ -17,6 +17,7 @@ Required properties:
    "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock)

(required)
    "core"    - SDC MMC clock (MCLK) (required)
    "bus"    - SDCC bus voter clock (optional)
+- clk-rates: Array of supported GCC clock frequencies for sdhc,
Units - Hz.

Why not use OPPv2 binding for this? We already have a way to
express frequencies for devices with that binding, and we'll need
to attach voltages to those frequencies at some point in the
future if we want to handle DVFS on these devices.

OPPv2 may not work out in this case. This was also discussed at [1].
These clk-rates are not as per voltage points(or any OPP) but as per
bus speed mode request from higher layer.

That post you link to had a response from Andy that echoed the
same sentiment and then no reply.

Are they a set of frequencies the device can operate at? Yes. Do
they have associated voltages that aren't expressed in this
patch? Yes.

Perhaps I've missed something though and the index of the array
of rates corresponds to some bus speed mode? That isn't clearly
expressed in the binding. Do the frequencies come from some spec
for those bus speed modes? Either way, I'd like to understand why
we need to put frequency tables into DT (hint: the commit text
should explain that).

As discussed offline, I will get back on this.

Regards
Ritesh