Re: [PATCH 3/4] clk: tegra: Correct bit width for PMC output clock mux

On Tue, Aug 02, 2016 at 11:34:28AM +0100, Jon Hunter wrote:

The bit field for setting the clock mux for the PMC output clocks is a
2-bit field and has always been a 2-bit field for all Tegra devices that
have these clocks (starting with Tegra30). However, the PMC clock driver
incorrectly specifies that this bit field is 3 bits wide and this causes
other bits in the register to be over-written when setting up the mux.
Therefore, correct the width for PMC clock mux to prevent over-writing
other fields.

Signed-off-by: Jon Hunter <redacted>
---

I did not bother marking this for stable because it has been around for
such a long time I don't think that this has caused any problems. I only
stumbled across this when dumping the register contents during some
testing. Nonetheless we should correct this.

 drivers/clk/tegra/clk-tegra-pmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.

Thierry