On Sat, Jul 30, 2016 at 04:25:47PM +0200, Hans de Goede wrote:

It turns out that sun4i (A10) and sun5i (A13 & co) do not have sample
clocks, so add a new sun7i-a20-mmc compatible and do not try to use
sample clocks on sun4i / sun5i.

Since sun4i / sun5i do not have sample clocks, they cannot (reliably) do
DDR rates, so only set MMC_CAP_1_8V_DDR when we do have sample clks.

Note this patch leaves the clk_prepare_enable() / clk_disable_unprepare()
calls to the sample clks as-is, without adding checks for them being
NULL. All the clk_foo calls accept a NULL clk and will return success when
called with a NULL clk.

Signed-off-by: Hans de Goede <redacted>
---
Changes in v2:
-Add a new sun7i-a20-compatible for SoCs with sample clks, rather then
 making them optional
---
 .../devicetree/bindings/mmc/sunxi-mmc.txt          |  6 +++-

I find the subject a bit strange as it should describe the change, not 
the problem. Otherwise,

Acked-by: Rob Herring <robh@kernel.org>

 drivers/mmc/host/sunxi-mmc.c                       | 35 +++++++++++++++-------
 2 files changed, 29 insertions(+), 12 deletions(-)