Re: [PATCH v4 1/2] tpm: devicetree: document properties for cr50
From: Jarkko Sakkinen <hidden>
Date: 2016-08-09 10:08:36
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On Thu, Jul 28, 2016 at 06:55:13PM -0700, Andrey Pronin wrote:
Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Signed-off-by: Andrey Pronin <redacted>
Acked-by: Jarkko Sakkinen <jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> /Jarkko
quoted hunk ↗ jump to hunk
--- .../devicetree/bindings/security/tpm/cr50_spi.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txtdiff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..2fbebd3 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt@@ -0,0 +1,21 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + }; +};-- 2.6.6
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