[PATCH v4 1/2] of: add J-Core timer bindings
From: Rich Felker <dalias@libc.org>
Date: 2016-07-27 05:35:31
Also in:
linux-sh, lkml
Subsystem:
clocksource, clockevent drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Daniel Lezcano, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Signed-off-by: Rich Felker <dalias@libc.org> --- .../devicetree/bindings/timer/jcore,pit.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
new file mode 100644
index 0000000..0f42af4
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt@@ -0,0 +1,25 @@ +J-Core Programmable Interval Timer and Clocksource + +Required properties: + +- compatible: Must be "jcore,pit". + +- reg: Memory region(s) for timer/clocksource registers. For SMP, + there should be one region per cpu, indexed by the sequential, + zero-based hardware cpu number (which is also the logical cpu + number). + +- interrupts: An interrupt to assign for the timer. The actual pit + core is integrated with the aic and allows the timer interrupt + assignment to be programmed by software, but this property is + required in order to reserve an interrupt number that doesn't + conflict with other devices. + + +Example: + +timer@200 { + compatible = "jcore,pit"; + reg = < 0x200 0x30 0x500 0x30 >; + interrupts = < 0x48 >; +};
--
2.8.1