Thread (3 messages) 3 messages, 3 authors, 2016-06-20

Re: [RFC PATCH 12/13] arm64: tegra: Add sor-safe clock to DPAUX binding

From: Jon Hunter <jonathanh@nvidia.com>
Date: 2016-06-20 09:23:38
Also in: dri-devel, linux-gpio, linux-i2c, linux-tegra

On 17/06/16 17:47, Thierry Reding wrote:
* PGP Signed by an unknown key

On Fri, Jun 17, 2016 at 01:03:46PM +0100, Jon Hunter wrote:
quoted
Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require
this clock for operation. Update the compatability string for the DPAUX
instance at address 0x545c0000 to be "nvidia,tegra210-dpaux" to ensure
that the 'sor-safe' clock is enabled for this device.
Does the second DPAUX need this, too? I have a vague recollection that
they were both slightly different.
I have assumed so, but I am checking with the h/w folks on this. Right
now the TRM only describes the procedure for configuring the DPAUX pads
for i2c6. I am also asking about sharing the DPAUX1 pads with i2c4.

Cheers
Jon

-- 
nvpublic
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