[RFC PATCH 12/13] arm64: tegra: Add sor-safe clock to DPAUX binding
From: Jon Hunter <jonathanh@nvidia.com>
Date: 2016-06-17 12:03:46
Also in:
dri-devel, linux-gpio, linux-i2c, linux-tegra
Subsystem:
the rest · Maintainer:
Linus Torvalds
Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require this clock for operation. Update the compatability string for the DPAUX instance at address 0x545c0000 to be "nvidia,tegra210-dpaux" to ensure that the 'sor-safe' clock is enabled for this device. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 94f780b43037..78bcc87b627d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi@@ -30,8 +30,9 @@ reg = <0x0 0x54040000 0x0 0x00040000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "dpaux", "parent", "sor-safe"; resets = <&tegra_car 207>; reset-names = "dpaux"; power-domains = <&pd_sor>;
@@ -175,12 +176,13 @@ }; dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; + compatible = "nvidia,tegra210-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "dpaux", "parent", "sor-safe"; resets = <&tegra_car 181>; reset-names = "dpaux"; power-domains = <&pd_sor>;
--
2.1.4