Re: [PATCH V8 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver.
From: Marek Vasut <hidden>
Date: 2016-02-10 16:17:33
On 02/10/2016 05:10 PM, Graham Moore wrote:
On 02/08/2016 09:27 AM, Marek Vasut wrote:quoted
On Monday, February 08, 2016 at 12:19:25 PM, Vignesh R wrote:quoted
On 02/06/2016 01:12 PM, Marek Vasut wrote:quoted
On Thursday, February 04, 2016 at 06:30:27 PM, R, Vignesh wrote:quoted
On 2/4/2016 4:55 PM, Marek Vasut wrote:[...]quoted
quoted
Yeah, there is delay(of few ns) required between writing to INDIRECTWR_START bit and actually writing data to flash(i.e writesl() call). This is specific to TI K2G SoC and needs to be tied to the new binding.Can't you somehow poll the hardware to check whether or not it's ready instead of adding some random delay ?There is no dedicated register to poll as such. According to TRM: "Wait for couple of cycles of QSPI_REF_CLK(functional clock of QSPI @384MHz) until CQSPI_REG_INDIRECTWR[0] bit is internally synchronized by the QSPI module before writing to flash". So, a few ns(~6ns @384MHz) delay is needed (or accessing a QSPI module register should be sufficient as it will take more than 2 clock cycles). I believe this delay is specific to TI K2G SoC and maybe needs to be tied to the binding.OK, got it. Dinh/Graham, can you check if this might be needed on SoCFPGA too please?I don't see any such requirement in the data sheet. It's working without it. So I think it's not needed on SoCFPGA
All right, so we will just add a special property or compat string for the TI SoC. But we need to get this driver mainlined first :) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html