[RFC v3 08/14] MIPS: dts: qca: introduce AR9331 devicetree
From: Antony Pavlov <hidden>
Date: 2016-01-23 20:17:25
Also in:
linux-mips
Subsystem:
mips, the rest · Maintainers:
Thomas Bogendoerfer, Linus Torvalds
Possibly related (same subject, not in this thread)
- 2016-03-14 · Re: [RFC v3 08/14] MIPS: dts: qca: introduce AR9331 devicetree · Antony Pavlov <hidden>
- 2016-01-31 · Re: [RFC v3 08/14] MIPS: dts: qca: introduce AR9331 devicetree · Antony Pavlov <hidden>
- 2016-01-25 · Re: [RFC v3 08/14] MIPS: dts: qca: introduce AR9331 devicetree · Alban <hidden>
This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet). The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC), typically used in very cheap Access Points and Routers. Signed-off-by: Antony Pavlov <redacted> Cc: Gabor Juhos <redacted> Cc: Alban Bedel <redacted> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org --- arch/mips/boot/dts/qca/ar9331.dtsi | 123 +++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+)
diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi
new file mode 100644
index 0000000..bf128a2
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331.dtsi@@ -0,0 +1,123 @@ +#include <dt-bindings/clock/ath79-clk.h> + +/ { + compatible = "qca,ar9331"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + cpuintc: interrupt-controller { + compatible = "qca,ar7100-cpu-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + + qca,ddr-wb-channel-interrupts = <2>, <3>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>; + }; + + extosc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&cpuintc>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&miscintc>; + + ddr_ctrl: memory-controller@18000000 { + compatible = "qca,ar7240-ddr-controller"; + reg = <0x18000000 0x100>; + + #qca,ddr-wb-channel-cells = <1>; + }; + + uart: uart@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + + interrupts = <3>; + + clocks = <&pll ATH79_CLK_UART>; + clock-names = "uart"; + + status = "disabled"; + }; + + gpio: gpio@18040000 { + compatible = "qca,ar7100-gpio"; + reg = <0x18040000 0x34>; + interrupts = <2>; + + ngpios = <30>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + status = "disabled"; + }; + + pll: pll-controller@18050000 { + compatible = "qca,ar9330-pll"; + reg = <0x18050000 0x20>; + + clocks = <&extosc>; + clock-names = "ref"; + + #clock-cells = <1>; + }; + + miscintc: interrupt-controller@18060010 { + compatible = "qca,ar7240-misc-intc"; + reg = <0x18060010 0x4>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + spi: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + clocks = <&pll ATH79_CLK_AHB>; + clock-names = "ahb"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + }; +};
--
2.6.2
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