Re: [PATCH 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk

On 23/11/15 07:02, Jonas Gorski wrote:

Hi,

On Sun, Nov 22, 2015 at 3:07 PM, Simon Arlott [off-list ref] wrote:

quoted

Instead of using a fixed clock HZ in the driver, obtain it from the
"periph" clk that the watchdog timer uses.

Signed-off-by: Simon Arlott <redacted>
---
 drivers/watchdog/bcm63xx_wdt.c | 36 +++++++++++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
index 1d2a501..eb5e551 100644
--- a/drivers/watchdog/bcm63xx_wdt.c
+++ b/drivers/watchdog/bcm63xx_wdt.c

@@ -13,6 +13,7 @@

 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

+#include <linux/clk.h>
 #include <linux/errno.h>
 #include <linux/io.h>
 #include <linux/kernel.h>

@@ -32,11 +33,13 @@

 #define PFX KBUILD_MODNAME

-#define WDT_HZ                 50000000                /* Fclk */
+#define WDT_CLK_NAME           "periph"

@Florian:
Is this correct? The comment for the watchdog in 6358_map_part.h and
earlier claims that the clock is 40 MHz there, but the code uses 50MHz
- is this a bug in the comments or is it a bug taken over from the
original broadcom code? I'm sure that the periph clock being 50 MHz
even on the older chips is correct, else we'd have noticed that in
serial output (where it's also used).

There are references to a Fbus2 clock in documentation, but I could not
find any actual documentation for its actual clock frequency, I would be
surprised if this chip would have diverged from the previous and future
ones and used a 40Mhz clock. 6345 started with a peripheral clock
running at 50Mhz, and that is true for all chips since then AFAICT.

I agree we would have noticed this with the UART or SPI controllers if
that was not true, so probably a code glitch here...
-- 
Florian
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