[PATCH 2/3] Documentation: DT: Add binding documentation for NVIDIA ADMA
From: Jon Hunter <hidden>
Date: 2015-09-25 14:56:39
Also in:
linux-tegra
Subsystem:
dma generic offload engine subsystem, open firmware and flattened device tree bindings, the rest · Maintainers:
Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Possibly related (same subject, not in this thread)
- 2015-09-25 · Re: [PATCH 2/3] Documentation: DT: Add binding documentation for NVIDIA ADMA · Mark Rutland <hidden>
Add device-tree binding documentation for the Tegra210 Audio DMA controller. Signed-off-by: Jon Hunter <redacted> --- .../devicetree/bindings/dma/tegra210-adma.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt
diff --git a/Documentation/devicetree/bindings/dma/tegra210-adma.txt b/Documentation/devicetree/bindings/dma/tegra210-adma.txt
new file mode 100644
index 000000000000..af04b3c5a557
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/tegra210-adma.txt@@ -0,0 +1,47 @@ +* NVIDIA Tegra Audio DMA controller + +Required properties: +- compatible: Should be "nvidia,<chip>-adma" +- reg: Should contain DMA registers location and length. This should include + all of the per-channel registers. +- interrupt-parent: Phandle to the interrupt parent controller. +- interrupts: Should contain all of the per-channel DMA interrupts. +- clocks: Must contain two entries, one for the power-domain clock and one + for the module clock. See ../clocks/clock-bindings.txt for details. +- dma-channels: Number of DMA channels supported by the controller. +- #dma-cells : Must be <0>. + +Examples: + +adma: adma@702e2000 { + compatible = "nvidia,tegra210-adma"; + reg = <0x0 0x702e2000 0x0 0x2000>; + interrupt-parent = <&tegra_agic>; + interrupts = <GIC_SPI INT_ADMA_EOT0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI INT_ADMA_EOT21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>, + <&tegra_car TEGRA210_CLK_ADMA_APE>; + clock-names = "adma", "adma.ape"; + dma-channels = <22>; + #dma-cells = <0>; +};
--
2.1.4