Re: [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts
From: Xing Zheng <hidden>
Date: 2015-09-24 02:20:39
Also in:
linux-arm-kernel, linux-rockchip, lkml
On 2015年09月17日 17:18, Heiko Stübner wrote:
Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng:quoted
Initial release for rk3036, node definitions rk3036 sdk board. Signed-off-by: Xing Zheng<redacted> --- Changes in v2: None arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3036-sdk.dts | 62 +++++++ arch/arm/boot/dts/rk3036.dtsi | 381 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 444 insertions(+) create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts create mode 100644 arch/arm/boot/dts/rk3036.dtsidiff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d39ce4b..48260c4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile@@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-bqcurie2.dtb \ rk3066a-marsboard.dtb \ rk3066a-rayeager.dtb \ + rk3036-sdk.dtb \ordering ... please put the rk3036 above rk3066 boards
Done.
quoted
rk3188-radxarock.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \diff --git a/arch/arm/boot/dts/rk3036-sdk.dtsb/arch/arm/boot/dts/rk3036-sdk.dts new file mode 100644 index 0000000..9187f93--- /dev/null +++ b/arch/arm/boot/dts/rk3036-sdk.dtsor "rk3036-evb.dts"? What is the actual board named?
Done, use rk3036-evb.dts
quoted
@@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015 Xing Zheng<zhengxing@rock-chips.com>this probably wants a Rockchip copyright notice?
Yes, remove this notice.
quoted
+ * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3036.dtsi" + +/ { + model = "SDK-RK3036"; + compatible = "sdk,sdk-rk3036", "rockchip,rk3036";model = "Rockchip RK3036-SDK"; compatible = "rockchip,rk3036-sdk", "rockchip,rk3036"; or model = "Rockchip RK3036 Evaluation board"; compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; depending on what the real board is labeled
Done.
quoted
+}; + +&i2c1 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg =<0x51>; + #clock-cells =<0>; + clock-frequency =<32768>; + clock-output-names = "xin32k"; + }; +}; \ No newline at end of filemissing newline as stated above
Done.
quoted
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi new file mode 100644 index 0000000..b7459c0 --- /dev/null +++ b/arch/arm/boot/dts/rk3036.dtsi@@ -0,0 +1,381 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include<dt-bindings/gpio/gpio.h> +#include<dt-bindings/interrupt-controller/irq.h> +#include<dt-bindings/interrupt-controller/arm-gic.h> +#include<dt-bindings/pinctrl/rockchip.h> +#include<dt-bindings/clock/rk3036-cru.h> +#include "skeleton.dtsi"in general, please sort nodes by register address, so for example interrupt-controller@10139000 should be before clock-controller@20000000 same for all other nodes
Done.
quoted
+ +/ { + compatible = "rockchip,rk3036"; + + interrupt-parent =<&gic>; + + aliases { + i2c1 =&i2c1; + serial0 =&uart0; + serial1 =&uart1; + serial2 =&uart2; + }; + + memory { + device_type = "memory"; + reg =<0x60000000 0x40000000>;ordering is possible ... to ease readability I try to keep this as compatible = ... reg = ... [other properties sorted alphabetically] status = ...
Done.
quoted
+ }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts =<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, +<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity =<&cpu0>,<&cpu1>; + };tabs, not spaces please
Done.
quoted
+ + cpus { + #address-cells =<1>; + #size-cells =<0>; + enable-method = "rockchip,rk3036-smp";this enable method is not yet defined, please don't add it until actual smp is accepted
Done, removed it on this patch.
quoted
+ + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg =<0xf00>; + operating-points =< + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells =<2>; /* min followed by max */again, not yet defined thermal handling, so the #cooling-cells should stay out for now
Done, removed it.
quoted
+ clock-latency =<40000>; + clocks =<&cru ARMCLK>; + resets =<&cru SRST_CORE0>; + }; + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg =<0xf01>; + resets =<&cru SRST_CORE1>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells =<1>; + #size-cells =<1>; + ranges; + + pdma: pdma@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg =<0x20078000 0x4000>; + interrupts =<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, +<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells =<1>; + clocks =<&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + };again tabs please
Done.
quoted
+ }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency =<24000000>; + clock-output-names = "xin24m"; + #clock-cells =<0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts =<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |IRQ_TYPE_LEVEL_HIGH)>,quoted
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, +quoted
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency =<24000000>; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg =<0x20000000 0x1000>; + rockchip,grf =<&grf>; + #clock-cells =<1>; + #reset-cells =<1>; + assigned-clocks =<&cru PLL_GPLL>; + assigned-clock-rates =<594000000>; + }; + + uart0: serial@20060000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg =<0x20060000 0x100>; + interrupts =<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift =<2>; + reg-io-width =<4>; + clock-frequency =<24000000>; + clocks =<&cru SCLK_UART0>,<&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 =<&uart0_xfer&uart0_cts&uart0_rts>;status = "disabled" and then in the board.dts a &uart0 { status = "okay"; }; not everybody will want to use uart0 ... same is true for the other two uarts.
Done.
quoted
+ }; + + uart1: serial@20064000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg =<0x20064000 0x100>; + interrupts =<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + reg-shift =<2>; + reg-io-width =<4>; + clock-frequency =<24000000>; + clocks =<&cru SCLK_UART1>,<&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 =<&uart1_xfer>; + }; + + uart2: serial@20068000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg =<0x20068000 0x100>; + interrupts =<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + reg-shift =<2>; + reg-io-width =<4>; + clock-frequency =<24000000>; + clocks =<&cru SCLK_UART2>,<&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 =<&uart2_xfer>; + }; + + pwm0: pwm@20050000 { + compatible = "rockchip,rk2928-pwm";compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; rk2928-pwm matches now, but if we find issues we can simply create the rk3036- pwm in the driver without needing to change the dts
Done.
quoted
+ reg =<0x20050000 0x10>; + #pwm-cells =<3>; + pinctrl-names = "default"; + pinctrl-0 =<&pwm0_pin>; + clocks =<&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@20050010 { + compatible = "rockchip,rk2928-pwm"; + reg =<0x20050010 0x10>; + #pwm-cells =<3>; + pinctrl-names = "default"; + pinctrl-0 =<&pwm1_pin>; + clocks =<&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg =<0x20050020 0x10>; + #pwm-cells =<3>; + pinctrl-names = "default"; + pinctrl-0 =<&pwm2_pin>; + clocks =<&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg =<0x20050030 0x10>; + #pwm-cells =<2>; + pinctrl-names = "default"; + pinctrl-0 =<&pwm3_pin>; + clocks =<&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + sram: sram@10080000 { + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; + reg =<0x10080000 0x2000>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells =<3>; + #address-cells =<0>; + + reg =<0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts =<GIC_PPI 9 0xf04>; + }; + + grf: syscon@20008000 { + compatible = "rockchip,rk3036-grf", "syscon"; + reg =<0x20008000 0x1000>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3036-pinctrl"; + rockchip,grf =<&grf>; + #address-cells =<1>; + #size-cells =<1>; + ranges; + + gpio0: gpio0@2007c000 { + compatible = "rockchip,gpio-bank"; + reg =<0x2007c000 0x100>; + interrupts =<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks =<&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells =<2>; + + interrupt-controller; + #interrupt-cells =<2>; + }; + + gpio1: gpio1@20080000 { + compatible = "rockchip,gpio-bank"; + reg =<0x20080000 0x100>; + interrupts =<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks =<&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells =<2>; + + interrupt-controller; + #interrupt-cells =<2>; + }; + + gpio2: gpio2@20084000 { + compatible = "rockchip,gpio-bank"; + reg =<0x20084000 0x100>; + interrupts =<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks =<&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells =<2>; + + interrupt-controller; + #interrupt-cells =<2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins =<0 16 RK_FUNC_1&pcfg_pull_none>,pcfg_pull_up for the rx-pin?
Done
quoted
+ <0 17 RK_FUNC_1&pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins =<0 18 RK_FUNC_1&pcfg_pull_none>; + };pcfg_pull_up again? see ARM: dts: rockchip: pull up cts lines on rk3288 (https://lkml.org/lkml/2015/9/2/612) for comparison
Yes, they should be pull up.
quoted
+ + uart0_rts: uart0-rts { + rockchip,pins =<0 19 RK_FUNC_1&pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins =<2 22 RK_FUNC_1&pcfg_pull_none>, + <2 23 RK_FUNC_1&pcfg_pull_none>; + }; + /* no rts / cts for uart1 */ + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins =<1 18 RK_FUNC_2 &pcfg_pull_none>, +<1 19 RK_FUNC_2&pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + };tabs please
Sorry, done.
quoted
+ + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins =<0 0 RK_FUNC_2&pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins =<0 1 RK_FUNC_2&pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins =<0 1 2&pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins =<0 27 1&pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins =<0 2 RK_FUNC_1&pcfg_pull_none>, + <0 3 RK_FUNC_1&pcfg_pull_none>; + }; + }; + }; + + i2c1: i2c@20056000 { + compatible = "rockchip,rk3288-i2c"; + reg =<0x20056000 0x1000>; + interrupts =<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells =<1>; + #size-cells =<0>; + clock-names = "i2c"; + clocks =<&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 =<&i2c1_xfer>; + status = "disabled"; + }; +};
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