Re: [PATCH v5 2/2] DT: i2c: Add binding document for IMG I2C SCB

On 11/10/2014 05:22 PM, Andrew Bresticker wrote:

Hi Ezequiel, James,

On Mon, Nov 10, 2014 at 11:30 AM, Ezequiel Garcia
[off-list ref] wrote:

quoted

From: James Hogan <redacted>

Introduce a devicetree binding for Imagination Technologies
I2C SCB controller.

Signed-off-by: James Hogan <redacted>
Signed-off-by: Ezequiel Garcia <redacted>

quoted

diff --git a/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt b/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt
new file mode 100644
index 0000000..3a5cd1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt

@@ -0,0 +1,29 @@
+IMG Serial Control Bus (SCB) I2C Controller
+
+Required Properties:
+- compatible: "img,scb-i2c"
+- reg: Physical base address and length of controller registers
+- interrupts: Interrupt number used by the controller
+- clocks : Should contain a clock specifier for each entry in clock-names
+- clock-names : Should contain the following entries:
+                "scb", for the SCB core clock.
+                "sys", for the system clock.
+- clock-frequency: The I2C bus frequency in Hz
+- #address-cells: Should be <1>
+- #size-cells: Should be <0>
+
+Optional Properties
+- img,bus-delay : Bus delay in ms, defaults to 0.

Maybe this is a dumb question, but what delay does this correspond to
in hardware?  In what situations would we use a non-zero value?

I'm not sure when would we need a non-zero value. The TRM I have here
mentions the bus delay parameter models the delay in the internal Clock
Enable Generation block, and which affects the values that should be
written to obtain a specified clock enable rate.

After re-reading the code that configures the clock generation, I think
we can use some more comments :)
-- 
Ezequiel