[PATCH/RFC 08/17] MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs
From: Kevin Cernekee <hidden>
Date: 2014-10-21 04:27:58
Also in:
linux-mips
Subsystem:
mips, the rest · Maintainers:
Thomas Bogendoerfer, Linus Torvalds
BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2 line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be cacheline-aligned and terrible things will happen. Signed-off-by: Kevin Cernekee <redacted> --- arch/mips/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 37b085c..38e02e1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig@@ -1587,12 +1587,14 @@ config CPU_BMIPS4350 config CPU_BMIPS4380 bool + select MIPS_L1_CACHE_SHIFT_6 select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU config CPU_BMIPS5000 bool select MIPS_CPU_SCACHE + select MIPS_L1_CACHE_SHIFT_7 select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU
--
2.1.1
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