On Tue, Sep 30, 2014 at 11:56:24PM +0800, Chen-Yu Tsai wrote:

On Tue, Sep 30, 2014 at 11:40 PM, Maxime Ripard
[off-list ref] wrote:

quoted

On Sat, Sep 27, 2014 at 04:49:49PM +0800, Chen-Yu Tsai wrote:

quoted

Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.

On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.

Isn't PLL6 having two childs as well?

No. It has one child, the normal PLL6 output clock.

The last "clock-output-names" entry refers to the factors clock itself,
in this case, the 2x clock output.

Hmmm, OK, I guess that's one way to see it too :)

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com