Hi Felipe,


On Tue, Oct 14, 2014 at 4:14 AM, Felipe Balbi [off-list ref] wrote:

Hi,

On Mon, Oct 13, 2014 at 01:54:59PM +0900, Anton Tikhomirov wrote:

quoted

Hi Vivek,

quoted

Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.

As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk is not enough.

quoted

Signed-off-by: Vivek Gautam <redacted>
---
 drivers/usb/dwc3/dwc3-exynos.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-

exynos.c
index 3951a65..7dc6a98 100644

--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c

@@ -35,6 +35,7 @@ struct dwc3_exynos {
    struct device           *dev;

    struct clk              *clk;

The clock "clk" in Exynos5 just gated all that above 7 clocks, which
we should control separately now in Exynos7.

should I drop this patch for now ?

Yes, better to hold this for some time till we get more clarity
from our h/w team.


-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India