Re: [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate
From: Thierry Reding <hidden>
Date: 2014-09-22 10:07:47
Also in:
dri-devel, linux-tegra
From: Thierry Reding <hidden>
Date: 2014-09-22 10:07:47
Also in:
dri-devel, linux-tegra
On Fri, Sep 19, 2014 at 03:53:48PM -0400, Sean Paul wrote:
Per NVidia, this clock rate should be around 70MHz in order to properly sample reads on data lane 0.
Can you point out where you get 70 MHz from? I only see the TRM mention 72 MHz that are needed for calibration. Also, what's the effect of doing this? Does it fix an issue that you're seeing? Thierry