On Tue, Sep 02, 2014 at 11:39:08AM +0100, Vivek Gautam wrote:

Hi,


On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland [off-list ref] wrote:

quoted

On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:

quoted

Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.

Signed-off-by: Vivek Gautam <redacted>
---
 drivers/usb/dwc3/dwc3-exynos.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index f9fb8ad..bab6395 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c

@@ -35,6 +35,7 @@ struct dwc3_exynos {
      struct device           *dev;

      struct clk              *clk;
+     struct clk              *sclk;
      struct regulator        *vdd33;
      struct regulator        *vdd10;
 };

@@ -141,10 +142,17 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
              return -EINVAL;
      }

+     /* Exynos7 has a special gate clock going to this IP */
+     exynos->sclk = devm_clk_get(dev, "usbdrd30_sclk");
+     if (IS_ERR(exynos->sclk))
+             dev_warn(dev, "couldn't get sclk\n");

Doesn't this introduce a pointless warning for Exynos SoCs other than
Exynos7?

True, it will introduce an unnecessary warning for non-Exynos7 systems.
I initially thought of introducing a compatible check for Exynos7-dwc3, but that
way we may end up adding such checks for future SoCs which have similar
controller but have some clock difference or some other small change, no ?

Perhaps. I don't know what your future hardware will look like.

Is the usbdrd30_sclk input unique to Exynos7, or was it previously there
but just without an input?

If the latter you could just reduce this to:

dev_info(dev, "no sclk specified");

Mark.