On Fri, Aug 22, 2014 at 10:54:50AM -0700, Sean Paul wrote:

On Thu, Aug 7, 2014 at 10:14 AM, Sean Paul [off-list ref] wrote:

quoted

On Thu, Aug 7, 2014 at 4:34 AM, Thierry Reding [off-list ref]
wrote:

quoted

On Thu, Aug 07, 2014 at 02:11:46AM -0400, Sean Paul wrote:

quoted

When calibrating the mipi phy, also include the clock lanes
in the calibration.

Signed-off-by: Sean Paul <redacted>
---
 drivers/gpu/host1x/mipi.c | 70

+++++++++++++++++++++++++++++++++++++----------

quoted

quoted

 1 file changed, 56 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
index 0af2892..80578dc 100644
--- a/drivers/gpu/host1x/mipi.c
+++ b/drivers/gpu/host1x/mipi.c

@@ -49,10 +49,18 @@
 #define MIPI_CAL_CONFIG_DSIC         0x10
 #define MIPI_CAL_CONFIG_DSID         0x11

+#define MIPI_CAL_CONFIG_DSIAB_CLK    0x19
+#define MIPI_CAL_CONFIG_DSICD_CLK    0x1a
+#define MIPI_CAL_CONFIG_CSIAB_CLK    0x1b
+#define MIPI_CAL_CONFIG_CSICD_CLK    0x1c
+#define MIPI_CAL_CONFIG_CSIE_CLK     0x1d
+

These registers don't seem to exist on Tegra114 and earlier. It also
seems like MIPI_CAL_CONFIG_DSIC and MIPI_CAL_CONFIG_DSID no longer exist
on Tegra124 and later. And CSIC and CSID seem to be shared with DSIB
(channel A and B) now.

So I think we'll need something more elaborate than this. It should be
differentiating between SoC revisions to allow checking for valid pad
selection when calibrating.

Yeah, definitely now that you point that out, we'll need something
better. I've altered the patch so the regs available depends on
compatible value. I'll wait on the following before re-posting.

quoted

I'll see if I can find out what's up with the change between Tegra114
and Tegra124 regarding the DSIC and DSID pads. It looks to me like they
were merged to match the DSIA and DSIB controllers, whereas before DSIA
and DSIB were used for controller DSIA and DSIC and DSID were used for
controller DSIB.

Thanks for checking in on this. It would be useful to know which clock
lanes need to be configured for which pads. The documentation isn't
particularly good on this, so it's possible that my mapping between
data lane/clock lane in the modules array is incorrect.

Hi Thierry,
Any update on this?

I don't have any definitive answers yet, but from doing a bit of
research it seems that the D-PHY for DSI (and CSI) can be configured to
run in two modes, one where the 4 lanes are used as a single channel and
another where they can drive two channels. My understanding is that that
is what the channels refer to. That is, the D-PHY for controller DSI is
calibrated using the MIPI_CAL_CONFIG_DSIA register (0x0e/0x38) for data
lanes and MIPI_CAL_CONFIG_DSIA_A (0x19/0x64) and MIPI_CAL_CONFIG_DSIA_B
(0x1a/0x68) for clock lanes. For controller DSIB the registers are
MIPI_CAL_CONFIG_DSIB (0x0f/0x3c) and MIPI_CAL_CONFIG_DSIB_A (0x1b/0x6c)
as well as MIPI_CAL_CONFIG_DSIB_B (0x1c/0x70). The second controller
also shares the pads with CSIC and CSID.

As for the difference between Tegra114 and Tegra124 it seems that clock
lane calibration is new in Tegra124 (or perhaps it was done as part of
the data lane calibration on Tegra114), but DSIA and DSIB on Tegra114
refer to DSI channels A and B, whereas DSIC and DSID refer to channels A
and B of DSIB.

The above is still mostly guesswork, though perhaps more educated than
before. I've filed an internal bug to get confirmation from some of our
hardware engineers and clarify this in the TRM. I'll let you know when I
have more information.

Thierry