On Thu, Aug 7, 2014 at 4:11 AM, Thierry Reding [off-list ref] wrote:

On Thu, Aug 07, 2014 at 02:11:44AM -0400, Sean Paul wrote:

quoted

This patch adds a new parent clock to enable/disable the 72MHz
clock required for mipi calibration.

s/mipi/MIPI/ please. Also this doesn't explain why this change is
necessary. Doesn't MIPI D-PHY calibration work without this patch? It
sure does for me.

Hi Thierry,
Thanks for the prompt reviews.

It doesn't work for me on T132 without this additional clock. It seems
the source for mipi-cal has changed between T124 & T132 from PLL_OUT3
to CLK72MHZ, so that could be why it's working for you and not for me.

Furthermore you say 72 MHz clock, but the below uses PLL_P_OUT3 as the
parent in the example, yet PLL_P_OUT3 runs at 102 MHz on all of my
systems. What 72 MHz clock are you referring to?

This was just a bogus assumption on my part that PLL_P_OUT3 was to be
programmed to 72MHz on pre-T132 setups.

Also can this parent clock ever be anything other than PLL_P_OUT3? If
not it would probably be better to set that statically in the clock
initialization tables.

I'm not entirely certain how I'd set CLK72MHZ statically in the init
tables, could you elaborate? I can get it to work by re-parenting
mipi-cal to clk72mhz, however I'm not sure if that would break other
platforms.

My initial thought was to add a compatible = "nvidia,tegra132-mipi",
which then would require the parent to be present in the dt.

quoted

diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
index 9882ea1..4dd91fd 100644
--- a/drivers/gpu/host1x/mipi.c
+++ b/drivers/gpu/host1x/mipi.c

@@ -80,7 +80,8 @@ static const struct module {
 struct tegra_mipi {
      void __iomem *regs;
      struct mutex lock;
-     struct clk *clk;
+     struct clk *clk_parent;
+     struct clk *clk_mipi_cal;

I don't think the clk -> clk_mipi_cal rename is warranted here.

Will do.

Sean

Thierry