Re: [PATCH v2 6/7] ARM: dts: rockchip: add core rk3288 dtsi

Hi Heiko,

+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@500 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x500>;
+               };
+               cpu@501 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x501>;
+               };
+               cpu@502 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x502>;
+               };
+               cpu@503 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x503>;

I take it that we can only use one of these for the moment? I didn't see
the addition of any SMP code.

Or did I miss that?

[...]

+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+               clock-frequency = <24000000>;
+       };

Please say you don't need this clock-frequency property.

It's a work-around at best, and you won't be able to use Hyp properly.
I'd really like to discourage use of this property, especially as people
seem to set it regardless of whether the hardware's correct...

What's the state of CNTFREQ and CNTVOFF, and is there any chance that
these are sane?

Cheers,
Mark.
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