Re: [PATCH v4 6/6] ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI
From: <hidden>
Date: 2014-07-10 05:20:47
Also in:
linux-serial
Hi! I'm trying to get up to speed with everyone [ mostly Chen-Yu's ] work on the a23; I just got an "azpen a727". Maybe this is a bit off thread, but I'd really like to get a response... Maybe there is more/relevant information on linux-sunxi.org, but it seems to be down tonight. Regardless, on fresh a pull of wens's u-boot-sunxi repo,
$ make sun8i_config
yeilds nothing on any branch other than lichee-dev-a23... ... and lichee-dev-a23's config is looking for a relative path for the toolchain, i think that's what autoconf means by ".../gcc-linaro/!$#@$-gcc: no such file or !@#%" sun4i and sun5i work or wens's repo... I haven't tried anything in a subfolder of origin from linux-sunxi's repo... Is everyone on the working with same toolchain repo in ~? [ maybe thats on linux-sunxi.org ] Is this all I should need to current build u-boot.bin for a23? I've only worked on well supported / figured out already hardware before and it's also likely I'm missing more basic uboot board config details, so I greatly appreciate any time, feedback, and guidance. I can't wait to help!, and consider this documentation which I'm totally happy to wiki when its up again. Best, Ed On Wednesday, July 9, 2014 3:54:50 AM UTC-4, Chen-Yu Tsai wrote:
quoted hunk
With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle. Signed-off-by: Chen-Yu Tsai <we...-jdAy2FN1RRM@public.gmane.org <javascript:>> --- arch/arm/boot/dts/sun8i-a23.dtsi | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-)diff --git a/arch/arm/boot/dts/sun8i-a23.dtsib/arch/arm/boot/dts/sun8i-a23.dtsi index 886776d..54ac0787 100644--- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi@@ -285,13 +285,58 @@ interrupts = <1 9 0xf04>; }; + prcm@01f01400 { + compatible = "allwinner,sun8i-a23-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible ="allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun8i-a23-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_timer", + "apb0_rsb", "apb0_uart", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + r_uart: serial@01f02800 { compatible = "snps,dw-apb-uart"; reg = <0x01f02800 0x400>; interrupts = <0 38 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb0_gates 4>; + resets = <&apb0_rst 4>; status = "disabled"; }; }; -- 2.0.1
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