[PATCH v2 2/2] arm64: Fix the APM X-Gene SoC SATA PHY clock DTS node csr-mask of the SATA Host Controller 1.
From: Suman Tripathi <hidden>
Date: 2014-07-10 13:50:23
Also in:
linux-ide, linux-scsi
Subsystem:
the rest · Maintainer:
Linus Torvalds
This patch fixes the SATA PHY clock DTS node csr-mask of the SATA Host controller 1. This patch also fixes the status of the PHY clock node of SATA Host Controller 1. Signed-off-by: Loc Ho <redacted> Signed-off-by: Suman Tripathi <redacted> --- arch/arm64/boot/dts/apm-storm.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index f8c40a6..ce6967c 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi@@ -184,9 +184,8 @@ reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy1clk"; - status = "disabled"; csr-offset = <0x4>; - csr-mask = <0x00>; + csr-mask = <0x3a>; enable-offset = <0x0>; enable-mask = <0x06>; };
@@ -198,7 +197,6 @@ reg = <0x0 0x1f22c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy2clk"; - status = "ok"; csr-offset = <0x4>; csr-mask = <0x3a>; enable-offset = <0x0>;
@@ -212,7 +210,6 @@ reg = <0x0 0x1f23c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy3clk"; - status = "ok"; csr-offset = <0x4>; csr-mask = <0x3a>; enable-offset = <0x0>; --
1.8.2.1