Re: [STLinux Kernel] [PATCH RESEND 05/12] drivers: clk: st: STiH407: Support for clockgenA0

On 5 June 2014 13:57, Peter Griffin [off-list ref] wrote:

Hi Gabi,

On Wed, 04 Jun 2014, Gabriel FERNANDEZ wrote:

quoted

The patch added support for DT registration of ClockGenA0
It includes c32 type PLL.

Signed-off-by: Gabriel Fernandez <redacted>
Signed-off-by: Olivier Bideau <redacted>
---
 drivers/clk/st/clkgen-pll.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8b9b1a..6916cfa 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c

@@ -180,6 +180,18 @@ static struct clkgen_pll_data st_pll1200c32_gpu_416 = {
      .ops            = &st_pll1200c32_ops,
 };

+static struct clkgen_pll_data st_pll3200c32_407_a0 = {
+     /* 407 A0 */
+     .pdn_status     = CLKGEN_FIELD(0x2a0,   0x1,                    8),
+     .locked_status  = CLKGEN_FIELD(0x2a0,   0x1,                    24),
+     .ndiv           = CLKGEN_FIELD(0x2a4,   C32_NDIV_MASK,          16),
+     .idf            = CLKGEN_FIELD(0x2a4,   C32_IDF_MASK,           0x0),
+     .num_odfs = 1,
+     .odf            = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK,           0) },
+     .odf_gate       = { CLKGEN_FIELD(0x2b4, 0x1,                    6) },
+     .ops            = &stm_pll3200c32_ops,
+};
+
 /**

I think these could be 'static const' as well, with some fixups in the function protoypes
which use it.

Done
Thanks Peter

Apart from that : -
 Acked-by: Peter Griffin [off-list ref]

Regards,

Peter