The PLL6 clock driver actually manages the PLL6x2 output of PLL6, so
rename the node accordingly, and add a halved fixed-factor-clock for
normal PLL6 output used by most modules.

Signed-off-by: Chen-Yu Tsai <redacted>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index a9dfa12..12d558b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi

@@ -94,11 +94,20 @@
 			clock-output-names = "pll1";
 		};
 
-		pll6: clk@01c20028 {
+		pll6x2: clk@01c20028 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-pll6-clk";
 			reg = <0x01c20028 0x4>;
 			clocks = <&osc24M>;
+			clock-output-names = "pll6x2";
+		};
+
+		pll6: pll6_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&pll6x2>;
 			clock-output-names = "pll6";
 		};