Re: [PATCH 1/2] regulator: pfuze100: Support SWB enable/disable

On 26/5/2014 10:57 PM, Mark Brown wrote:

On Mon, May 26, 2014 at 04:45:40PM +0800, Sean Cross wrote:

quoted

+			.enable_reg = (base),	\
+			.enable_mask = 0x48,	\

I note that this is a two bit field - what do the two bits mean?

The datasheet defines the register SWBST Control 1 as having the 
following bit values:

   xbbx mmvv

Where:
     x = don't care
     b = SWBST1STBYMODE[1:0]
     m = SWBST1MODE[1:0]
     v = SWBST1VOLT[1:0]

Both SWBST1STBYMODE and SWBST1MODE have the same bit meanings.  In this 
case, they're both getting set to 0b10, which means "Auto". That is, 
they'll automatically switch between PFM and PWM mode for regulation 
depending on load.

Other regulators, such as the VGEN regulators, don't set their 
corresponding VGENxSTBY bit, which means they will remain on even when 
the STANDBY line is asserted.  By setting both SWBST1STBYMODE and 
SWBST1MODE, the SWBST regulator behaves the same way.


Sean
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