Thread (1 message) 1 message, 1 author, 2014-01-24

RE: [PATCH] clk: corenet: Update the clock bindings

From: Yuantian Tang <hidden>
Date: 2014-01-24 02:33:19
Also in: linuxppc-dev

Possibly related (same subject, not in this thread)

quoted
quoted
Instead, how about a note like this near the top of the file:

All references to "1.0" and "2.0" refer to the QorIQ chassis version
to which the chip complies.

Chassis Version		Example Chips
---------------		-------------
1.0			p4080, p5020, p5040
2.0			t4240, b4860, t1040
Better, I will update.
quoted
BTW, this binding and the associated driver really should be called
"qoriq-clock", not "corenet-clock".  This would match the compatible
string, and it doesn't really have much to do with corenet (which is
part of the QorIQ chassis v1 and v2, but not *this* part).  Do you
know if the chassis v3 clock interface will be similar enough to
share a driver?
quoted
quoted
Doesn't QorIQ include some low-end socs, like p1022, p1020?
Yes, but those aren't "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0".
They're mpc85xx-family chips.

In any case, if "qoriq" makes sense for the compatible, I don't see why
it doesn't make sense for the driver.
So, "Corenet" is appropriate for driver.
If something should change, that must be compatible string.

Regards,
Yuantian
quoted
This driver has nothing to do with these boards.
I have no idea about chassis v3. If it has similar clock tree, this
driver can be shared.
quoted
Even the driver can't be used by v3, we can easily add v3 support
since it has different Compatible string.
The reason I mentioned it is that chassis v3 will involve ARM chips that
have their own interconnect rather than corenet.

-Scott
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