Re: [PATCH] clk: corenet: Update the clock bindings
From: Scott Wood <hidden>
Date: 2014-01-23 00:44:23
Also in:
linuxppc-dev
On Tue, 2014-01-21 at 10:02 +0800, Tang Yuantian wrote:
quoted hunk
From: Tang Yuantian <redacted> Main changs include: - Clarified the clock nodes' version number - Fixed a issue in example Singed-off-by: Tang Yuantian [off-list ref] --- Documentation/devicetree/bindings/clock/corenet-clock.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt index 24711af..d6cadef 100644 --- a/Documentation/devicetree/bindings/clock/corenet-clock.txt +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt@@ -54,6 +54,8 @@ Required properties: It takes parent's clock-frequency as its clock. * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). It takes parent's clock-frequency as its clock. + Note: v1.0 and v2.0 are clock version which should align to + clockgen node's they belong to which is chassis version.
Instead, how about a note like this near the top of the file: All references to "1.0" and "2.0" refer to the QorIQ chassis version to which the chip complies. Chassis Version Example Chips --------------- ------------- 1.0 p4080, p5020, p5040 2.0 t4240, b4860, t1040 BTW, this binding and the associated driver really should be called "qoriq-clock", not "corenet-clock". This would match the compatible string, and it doesn't really have much to do with corenet (which is part of the QorIQ chassis v1 and v2, but not *this* part). Do you know if the chassis v3 clock interface will be similar enough to share a driver? -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html