Re: [PATCHv9 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"
From: Arnd Bergmann <arnd@arndb.de>
Date: 2014-01-10 19:00:25
Also in:
linux-arm-kernel, linux-mmc
On Friday 10 January 2014, Dinh Nguyen wrote:
quoted
quoted
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f936476..e776512 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi@@ -413,6 +413,7 @@ compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>,<&per_nand_mmc_clk>; clk-gate = <0xa0 8>; + clk-phase = <0 135>;Can clk-phase be applicable commonly for various board? Isn't specific timing values?No, the clock-phase does not change for various board. It is a SoC-specific property.
I'm curious about this: If the setting is fixed per soc, why is it even configurable, rather than hardwired to the correct setting, or set up by the boot loader? Arnd