Re: gpio: dwapb: Synopsys Designware GPIO

On Thu, Oct 31, 2013 at 05:17:39PM +0100, Steffen Trumtrar wrote:

On Thu, Oct 31, 2013 at 04:07:23PM +0000, Jamie Iles wrote:

quoted

The reason for having it split into banks is that for hardware that 
has a mixture of bank sizes (odd hardware admittedly, but that 
includes hardware that I was writing the driver for), we had a setup 
like 16 pins on bank A, 16 on B, 1 on C and 16 on D where each bank 
could have a maximum of 32, so converting from a data sheet to GPIO 
number is not obvious.  Grant Likely suggested representing the 
banks as different devices, so that's how I created the binding.

I have no problem with the binding, if it is worth it. Do you mean you had
hardware where the gpio lines where not connected? Or maybe you had an older
version of the IP core?

Not even unconnected, the IP was configured to have banks of varying 
width!  Perhaps it was something to do with the physical pads that they 
were connected to having different I/O standards or something.

In the Socfpga case there is gpio_config_reg2, which specifies the width
for every of the 4 ports. So I thought I use those values to describe my
hardware. The Socfpga however only uses the first bank of its three GPIO cores,
so I wouldn't be able to test if the code works for more than just that.

I think that if there was a guarantee that all banks apart from the last 
were configured to equal width then representing the controller as a 
single device would be right, but given that it isn't always the case 
then seperate devices for each bank is probably the most sensible.

That said I'd personally be happy either way to see the patches merged!

Jamie
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