@@ -36,8 +36,12 @@ Optional properties: "prefetch-dma" Prefetch enabled sDMA mode "prefetch-irq" Prefetch enabled irq mode- - elm_id: Specifies elm device node. This is required to support BCH- error correction using ELM module.+ - elm_id: <deprecated> use "ti,elm-id" instead+ - ti,elm-id: Specifies phandle of the ELM devicetree node.+ ELM is an on-chip hardware engine on TI SoC which is used for+ locating ECC errors for BCHx algorithms. SoC devices which have+ ELM hardware engines should specify this device node in .dtsi+ Using ELM for ECC error correction frees some CPU cycles. For inline partiton table parsing (optional):
@@ -1378,13 +1370,41 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,gpmc_nand_data->cs=val;gpmc_nand_data->of_node=child;-if(!of_property_read_string(child,"ti,nand-ecc-opt",&s))-for(val=0;val<ARRAY_SIZE(nand_ecc_opts);val++)-if(!strcasecmp(s,nand_ecc_opts[val])){-gpmc_nand_data->ecc_opt=val;-break;-}+/* Detect availability of ELM module */+gpmc_nand_data->elm_of_node=of_parse_phandle(child,"ti,elm-id",0);+if(gpmc_nand_data->elm_of_node==NULL)+gpmc_nand_data->elm_of_node=+of_parse_phandle(child,"elm_id",0);+if(gpmc_nand_data->elm_of_node==NULL)+pr_warn("%s: ti,elm-id property not found\n",__func__);++/* select ecc-scheme for NAND */+if(of_property_read_string(child,"ti,nand-ecc-opt",&s)){+pr_err("%s: ti,nand-ecc-opt not found\n",__func__);+return-ENODEV;+}+if(!strcmp(s,"ham1")||!strcmp(s,"sw")||+!strcmp(s,"hw")||!strcmp(s,"hw-romcode"))+gpmc_nand_data->ecc_opt=+OMAP_ECC_HAM1_CODE_HW;+elseif(!strcmp(s,"bch4"))+if(gpmc_nand_data->elm_of_node)+gpmc_nand_data->ecc_opt=+OMAP_ECC_BCH4_CODE_HW;+else+gpmc_nand_data->ecc_opt=+OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;+elseif(!strcmp(s,"bch8"))+if(gpmc_nand_data->elm_of_node)+gpmc_nand_data->ecc_opt=+OMAP_ECC_BCH8_CODE_HW;+else+gpmc_nand_data->ecc_opt=+OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;+else+pr_err("%s: ti,nand-ecc-opt invalid value\n",__func__);+/* select data transfer mode for NAND controller */if(!of_property_read_string(child,"ti,nand-xfer-type",&s))for(val=0;val<ARRAY_SIZE(nand_xfer_types);val++)if(!strcasecmp(s,nand_xfer_types[val])){
@@ -28,8 +28,16 @@ enum omap_ecc {OMAP_ECC_HAMMING_CODE_HW,/* gpmc to detect the error *//* 1-bit ecc: stored at beginning of spare area as romcode */OMAP_ECC_HAMMING_CODE_HW_ROMCODE,/* gpmc method & romcode layout */-OMAP_ECC_BCH4_CODE_HW,/* 4-bit BCH ecc code */-OMAP_ECC_BCH8_CODE_HW,/* 8-bit BCH ecc code */+/* 1-bit ECC calculation by GPMC, Error detection by Software */+OMAP_ECC_HAM1_CODE_HW,+/* 4-bit ECC calculation by GPMC, Error detection by Software */+OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,+/* 4-bit ECC calculation by GPMC, Error detection by ELM */+OMAP_ECC_BCH4_CODE_HW,+/* 8-bit ECC calculation by GPMC, Error detection by Software */+OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,+/* 8-bit ECC calculation by GPMC, Error detection by ELM */+OMAP_ECC_BCH8_CODE_HW,};structgpmc_nand_regs{
@@ -63,5 +71,6 @@ struct omap_nand_platform_data {/* for passing the partitions */structdevice_node*of_node;+structdevice_node*elm_of_node;};#endif
@@ -1993,10 +1993,7 @@ static int omap_nand_probe(struct platform_device *pdev)}/* select the ecc type */-if(pdata->ecc_opt==OMAP_ECC_HAMMING_CODE_DEFAULT)-info->nand.ecc.mode=NAND_ECC_SOFT;-elseif((pdata->ecc_opt==OMAP_ECC_HAMMING_CODE_HW)||-(pdata->ecc_opt==OMAP_ECC_HAMMING_CODE_HW_ROMCODE)){+if(pdata->ecc_opt==OMAP_ECC_HAM1_CODE_HW){info->nand.ecc.bytes=3;info->nand.ecc.size=512;info->nand.ecc.strength=1;
@@ -2025,7 +2022,7 @@ static int omap_nand_probe(struct platform_device *pdev)}/* rom code layout */-if(pdata->ecc_opt==OMAP_ECC_HAMMING_CODE_HW_ROMCODE){+if(pdata->ecc_opt==OMAP_ECC_HAM1_CODE_HW){if(info->nand.options&NAND_BUSWIDTH_16)offset=2;
@@ -2033,7 +2030,7 @@ static int omap_nand_probe(struct platform_device *pdev)offset=1;info->nand.badblock_pattern=&bb_descrip_flashbased;}-omap_oobinfo.eccbytes=3*(info->mtd.oobsize/16);+omap_oobinfo.eccbytes=3*(info->mtd.writesize/512);for(i=0;i<omap_oobinfo.eccbytes;i++)omap_oobinfo.eccpos[i]=i+offset;
@@ -23,13 +23,8 @@ enum nand_io {};enumomap_ecc{-/* 1-bit ecc: stored at end of spare area */-OMAP_ECC_HAMMING_CODE_DEFAULT=0,/* Default, s/w method */-OMAP_ECC_HAMMING_CODE_HW,/* gpmc to detect the error */-/* 1-bit ecc: stored at beginning of spare area as romcode */-OMAP_ECC_HAMMING_CODE_HW_ROMCODE,/* gpmc method & romcode layout *//* 1-bit ECC calculation by GPMC, Error detection by Software */-OMAP_ECC_HAM1_CODE_HW,+OMAP_ECC_HAM1_CODE_HW=0,/* 4-bit ECC calculation by GPMC, Error detection by Software */OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,/* 4-bit ECC calculation by GPMC, Error detection by ELM */
@@ -1824,10 +1824,12 @@ static int omap_nand_probe(struct platform_device *pdev){structomap_nand_info*info;structomap_nand_platform_data*pdata;+structmtd_info*mtd;+structnand_chip*nand_chip;interr;inti,offset;-dma_cap_mask_tmask;-unsignedsig;+dma_cap_mask_tmask;+unsignedsig;structresource*res;structmtd_part_parser_datappdata={};
@@ -1846,17 +1848,16 @@ static int omap_nand_probe(struct platform_device *pdev)spin_lock_init(&info->controller.lock);init_waitqueue_head(&info->controller.wq);-info->pdev=pdev;-+info->pdev=pdev;info->gpmc_cs=pdata->cs;info->reg=pdata->reg;--info->mtd.priv=&info->nand;-info->mtd.name=dev_name(&pdev->dev);-info->mtd.owner=THIS_MODULE;--info->nand.options=pdata->devsize;-info->nand.options|=NAND_SKIP_BBTSCAN;+mtd=&info->mtd;+mtd->priv=&info->nand;+mtd->name=dev_name(&pdev->dev);+mtd->owner=THIS_MODULE;+nand_chip=&info->nand;+nand_chip->options=pdata->devsize;+nand_chip->options|=NAND_SKIP_BBTSCAN;#ifdef CONFIG_MTD_NAND_OMAP_BCHinfo->of_node=pdata->of_node;#endif
@@ -1877,16 +1878,16 @@ static int omap_nand_probe(struct platform_device *pdev)gotoout_free_info;}-info->nand.IO_ADDR_R=ioremap(info->phys_base,info->mem_size);-if(!info->nand.IO_ADDR_R){+nand_chip->IO_ADDR_R=ioremap(info->phys_base,info->mem_size);+if(!nand_chip->IO_ADDR_R){err=-ENOMEM;gotoout_release_mem_region;}-info->nand.controller=&info->controller;+nand_chip->controller=&info->controller;-info->nand.IO_ADDR_W=info->nand.IO_ADDR_R;-info->nand.cmd_ctrl=omap_hwcontrol;+nand_chip->IO_ADDR_W=nand_chip->IO_ADDR_R;+nand_chip->cmd_ctrl=omap_hwcontrol;/**IfRDY/BSYlineisconnectedtoOMAPthenusetheomapready
@@ -1896,26 +1897,26 @@ static int omap_nand_probe(struct platform_device *pdev)*deviceandreadstatusregisteruntilyougetafailureorsuccess*/if(pdata->dev_ready){-info->nand.dev_ready=omap_dev_ready;-info->nand.chip_delay=0;+nand_chip->dev_ready=omap_dev_ready;+nand_chip->chip_delay=0;}else{-info->nand.waitfunc=omap_wait;-info->nand.chip_delay=50;+nand_chip->waitfunc=omap_wait;+nand_chip->chip_delay=50;}switch(pdata->xfer_type){caseNAND_OMAP_PREFETCH_POLLED:-info->nand.read_buf=omap_read_buf_pref;-info->nand.write_buf=omap_write_buf_pref;+nand_chip->read_buf=omap_read_buf_pref;+nand_chip->write_buf=omap_write_buf_pref;break;caseNAND_OMAP_POLLED:-if(info->nand.options&NAND_BUSWIDTH_16){-info->nand.read_buf=omap_read_buf16;-info->nand.write_buf=omap_write_buf16;+if(nand_chip->options&NAND_BUSWIDTH_16){+nand_chip->read_buf=omap_read_buf16;+nand_chip->write_buf=omap_write_buf16;}else{-info->nand.read_buf=omap_read_buf8;-info->nand.write_buf=omap_write_buf8;+nand_chip->read_buf=omap_read_buf8;+nand_chip->write_buf=omap_write_buf8;}break;
@@ -1944,8 +1945,8 @@ static int omap_nand_probe(struct platform_device *pdev)err);gotoout_release_mem_region;}-info->nand.read_buf=omap_read_buf_dma_pref;-info->nand.write_buf=omap_write_buf_dma_pref;+nand_chip->read_buf=omap_read_buf_dma_pref;+nand_chip->write_buf=omap_write_buf_dma_pref;}break;
@@ -1980,8 +1981,8 @@ static int omap_nand_probe(struct platform_device *pdev)gotoout_release_mem_region;}-info->nand.read_buf=omap_read_buf_irq_pref;-info->nand.write_buf=omap_write_buf_irq_pref;+nand_chip->read_buf=omap_read_buf_irq_pref;+nand_chip->write_buf=omap_write_buf_irq_pref;break;
@@ -1994,16 +1995,16 @@ static int omap_nand_probe(struct platform_device *pdev)/* select the ecc type */if(pdata->ecc_opt==OMAP_ECC_HAM1_CODE_HW){-info->nand.ecc.bytes=3;-info->nand.ecc.size=512;-info->nand.ecc.strength=1;-info->nand.ecc.calculate=omap_calculate_ecc;-info->nand.ecc.hwctl=omap_enable_hwecc;-info->nand.ecc.correct=omap_correct_data;-info->nand.ecc.mode=NAND_ECC_HW;+nand_chip->ecc.bytes=3;+nand_chip->ecc.size=512;+nand_chip->ecc.strength=1;+nand_chip->ecc.calculate=omap_calculate_ecc;+nand_chip->ecc.hwctl=omap_enable_hwecc;+nand_chip->ecc.correct=omap_correct_data;+nand_chip->ecc.mode=NAND_ECC_HW;}elseif((pdata->ecc_opt==OMAP_ECC_BCH4_CODE_HW)||(pdata->ecc_opt==OMAP_ECC_BCH8_CODE_HW)){-err=omap3_init_bch(&info->mtd,pdata->ecc_opt);+err=omap3_init_bch(mtd,pdata->ecc_opt);if(err){err=-EINVAL;gotoout_release_mem_region;
@@ -2013,9 +2014,9 @@ static int omap_nand_probe(struct platform_device *pdev)/* DIP switches on some boards change between 8 and 16 bit*buswidthsforflash.Trytheotherwidthifthefirsttryfails.*/-if(nand_scan_ident(&info->mtd,1,NULL)){-info->nand.options^=NAND_BUSWIDTH_16;-if(nand_scan_ident(&info->mtd,1,NULL)){+if(nand_scan_ident(mtd,1,NULL)){+nand_chip->options^=NAND_BUSWIDTH_16;+if(nand_scan_ident(mtd,1,NULL)){err=-ENXIO;gotoout_release_mem_region;}
@@ -2024,25 +2025,25 @@ static int omap_nand_probe(struct platform_device *pdev)/* rom code layout */if(pdata->ecc_opt==OMAP_ECC_HAM1_CODE_HW){-if(info->nand.options&NAND_BUSWIDTH_16)+if(nand_chip->options&NAND_BUSWIDTH_16){offset=2;-else{+}else{offset=1;-info->nand.badblock_pattern=&bb_descrip_flashbased;+nand_chip->badblock_pattern=&bb_descrip_flashbased;}-omap_oobinfo.eccbytes=3*(info->mtd.writesize/512);+omap_oobinfo.eccbytes=3*(mtd->writesize/512);for(i=0;i<omap_oobinfo.eccbytes;i++)omap_oobinfo.eccpos[i]=i+offset;omap_oobinfo.oobfree->offset=offset+omap_oobinfo.eccbytes;-omap_oobinfo.oobfree->length=info->mtd.oobsize-+omap_oobinfo.oobfree->length=mtd->oobsize-(offset+omap_oobinfo.eccbytes);-info->nand.ecc.layout=&omap_oobinfo;+nand_chip->ecc.layout=&omap_oobinfo;}elseif((pdata->ecc_opt==OMAP_ECC_BCH4_CODE_HW)||(pdata->ecc_opt==OMAP_ECC_BCH8_CODE_HW)){/* build OOB layout for BCH ECC correction */-err=omap3_init_bch_tail(&info->mtd);+err=omap3_init_bch_tail(mtd);if(err){err=-EINVAL;gotoout_release_mem_region;
@@ -2050,16 +2051,16 @@ static int omap_nand_probe(struct platform_device *pdev)}/* second phase scan */-if(nand_scan_tail(&info->mtd)){+if(nand_scan_tail(mtd)){err=-ENXIO;gotoout_release_mem_region;}ppdata.of_node=pdata->of_node;-mtd_device_parse_register(&info->mtd,NULL,&ppdata,pdata->parts,+mtd_device_parse_register(mtd,NULL,&ppdata,pdata->parts,pdata->nr_parts);-platform_set_drvdata(pdev,&info->mtd);+platform_set_drvdata(pdev,mtd);return0;
@@ -1856,7 +1856,6 @@ static int omap_nand_probe(struct platform_device *pdev)mtd->name=dev_name(&pdev->dev);mtd->owner=THIS_MODULE;nand_chip=&info->nand;-nand_chip->options=pdata->devsize;nand_chip->options|=NAND_SKIP_BBTSCAN;#ifdef CONFIG_MTD_NAND_OMAP_BCHinfo->of_node=pdata->of_node;
@@ -1904,6 +1903,15 @@ static int omap_nand_probe(struct platform_device *pdev)nand_chip->chip_delay=50;}+/* scan NAND device connected to chip controller */+nand_chip->options|=pdata->devsize&NAND_BUSWIDTH_16;+if(nand_scan_ident(mtd,1,NULL)){+pr_err("nand device scan failed, may be bus-width mismatch\n");+err=-ENXIO;+gotoout_release_mem_region;+}++/* re-populate low-level callbacks based on xfer modes */switch(pdata->xfer_type){caseNAND_OMAP_PREFETCH_POLLED:nand_chip->read_buf=omap_read_buf_pref;
@@ -2011,17 +2019,6 @@ static int omap_nand_probe(struct platform_device *pdev)}}-/* DIP switches on some boards change between 8 and 16 bit-*buswidthsforflash.Trytheotherwidthifthefirsttryfails.-*/-if(nand_scan_ident(mtd,1,NULL)){-nand_chip->options^=NAND_BUSWIDTH_16;-if(nand_scan_ident(mtd,1,NULL)){-err=-ENXIO;-gotoout_release_mem_region;-}-}-/* rom code layout */if(pdata->ecc_opt==OMAP_ECC_HAM1_CODE_HW){
current implementation in omap3_init_bch() has some redundant code like:
(1) omap3_init_bch() re-probes the DT-binding to detect presence of ELM h/w
engine on SoC. And based on that it selects implemetation of ecc-scheme.
However, this is already done as part of GPMC DT parsing.
(2) As omap3_init_bch() serves as common function for configuring all types of
BCHx ecc-schemes, so there are multiple levels of redudant if..then..else
checks while populating nand_chip->ecc.
This patch make following changes to OMAP NAND driver:
(1) removes omap3_init_bch(): each ecc-scheme is individually configured in
omap_nand_probe() there by removing redundant if..then..else checks.
(2) adds is_elm_present(): re-probing of ELM device via DT is not required as
it's done in GPMC driver probe. Thus is_elm_present() just initializes ELM
driver with NAND probe data, when ecc-scheme with h/w based error-detection
is used.
(3) separates out configuration of different flavours of "BCH4" and "BCH8"
ecc-schemes as given in below table
(4) conditionally compiles callbacks implementations of ecc.hwctl(),
ecc.calculate(), ecc.correct() to avoid warning of un-used functions.
+---------------------------------------+---------------+---------------+
| ECC scheme |ECC calculation|Error detection|
+---------------------------------------+---------------+---------------+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id) | | |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id) | | |
+---------------------------------------+---------------+---------------+
- 'CONFIG_MTD_NAND_ECC_BCH' is generic KConfig required to build lib/bch.c
which is required for ECC error detection done in software.
(mainly used for legacy platforms which do not have on-chip ELM engine)
- 'CONFIG_MTD_NAND_OMAP_BCH' is OMAP specific Kconfig to detemine presence
on ELM h/w engine on SoC.
Signed-off-by: Pekon Gupta <redacted>
---
drivers/mtd/nand/omap2.c | 281 ++++++++++++++++++++++++++---------------------
1 file changed, 158 insertions(+), 123 deletions(-)
@@ -1637,118 +1642,48 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,}/**-*omap3_free_bch-ReleaseBCHeccresources-*@mtd:MTDdevicestructure+*is_elm_present-checksforpresenceofELMmodulebyscanningDTnodes+*@omap_nand_info:NANDdevicestructurecontainingplatformdata+*@bch_type:0x0=BCH4,0x1=BCH8,0x2=BCH16*/-staticvoidomap3_free_bch(structmtd_info*mtd)+staticintis_elm_present(structomap_nand_info*info,+structdevice_node*elm_node,enumbch_eccbch_type){-structomap_nand_info*info=container_of(mtd,structomap_nand_info,-mtd);-if(info->bch){-free_bch(info->bch);-info->bch=NULL;+structplatform_device*pdev;+info->is_elm_used=false;+/* check whether elm-id is passed via DT */+if(!elm_node){+pr_err("nand: error: ELM DT node not found\n");+return-ENODEV;+}+pdev=of_find_device_by_node(elm_node);+/* check whether ELM device is registered */+if(!pdev){+pr_err("nand: error: ELM device not found\n");+return-ENODEV;}+/* ELM module available, now configure it */+info->elm_dev=&pdev->dev;+if(elm_config(info->elm_dev,bch_type))+return-ENODEV;+info->is_elm_used=true;+return0;}+#endif /* CONFIG_MTD_NAND_ECC_BCH */+#ifdef CONFIG_MTD_NAND_ECC_BCH/**-*omap3_init_bch-InitializeBCHECC+*omap3_free_bch-ReleaseBCHeccresources*@mtd:MTDdevicestructure-*@ecc_opt:OMAPECCmode(OMAP_ECC_BCH4_CODE_HWorOMAP_ECC_BCH8_CODE_HW)*/-staticintomap3_init_bch(structmtd_info*mtd,intecc_opt)+staticvoidomap3_free_bch(structmtd_info*mtd){-intmax_errors;structomap_nand_info*info=container_of(mtd,structomap_nand_info,mtd);-#ifdef CONFIG_MTD_NAND_OMAP_BCH8-constinthw_errors=BCH8_MAX_ERROR;-#else-constinthw_errors=BCH4_MAX_ERROR;-#endif-enumbch_eccbch_type;-const__be32*parp;-intlenp;-structdevice_node*elm_node;--info->bch=NULL;--max_errors=(ecc_opt==OMAP_ECC_BCH8_CODE_HW)?-BCH8_MAX_ERROR:BCH4_MAX_ERROR;-if(max_errors!=hw_errors){-pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",-max_errors,hw_errors);-gotofail;-}--info->nand.ecc.size=512;-info->nand.ecc.hwctl=omap3_enable_hwecc_bch;-info->nand.ecc.mode=NAND_ECC_HW;-info->nand.ecc.strength=max_errors;--if(hw_errors==BCH8_MAX_ERROR)-bch_type=BCH8_ECC;-else-bch_type=BCH4_ECC;--/* Detect availability of ELM module */-parp=of_get_property(info->of_node,"elm_id",&lenp);-if((parp==NULL)&&(lenp!=(sizeof(void*)*2))){-pr_err("Missing elm_id property, fall back to Software BCH\n");-info->is_elm_used=false;-}else{-structplatform_device*pdev;--elm_node=of_find_node_by_phandle(be32_to_cpup(parp));-pdev=of_find_device_by_node(elm_node);-info->elm_dev=&pdev->dev;--if(elm_config(info->elm_dev,bch_type)==0)-info->is_elm_used=true;-}--if(info->is_elm_used&&(mtd->writesize<=4096)){--if(hw_errors==BCH8_MAX_ERROR)-info->nand.ecc.bytes=BCH8_SIZE;-else-info->nand.ecc.bytes=BCH4_SIZE;--info->nand.ecc.correct=omap_elm_correct_data;-info->nand.ecc.calculate=omap3_calculate_ecc_bch;-info->nand.ecc.read_page=omap_read_page_bch;-info->nand.ecc.write_page=omap_write_page_bch;-}else{-/*-*softwarebchlibraryisonlyusedtodetectand-*locateerrors-*/-info->bch=init_bch(13,max_errors,-0x201b/* hw polynomial */);-if(!info->bch)-gotofail;--info->nand.ecc.correct=omap3_correct_data_bch;--/*-*Thenumberofcorrectederrorsinaneccblockthatwill-*triggerblockscrubbingdefaultstotheeccstrength(4or8)-*Setmtd->bitflip_thresholdheretodefineacustomthreshold.-*/--if(max_errors==8){-info->nand.ecc.bytes=13;-info->nand.ecc.calculate=omap3_calculate_ecc_bch8;-}else{-info->nand.ecc.bytes=7;-info->nand.ecc.calculate=omap3_calculate_ecc_bch4;-}+if(info->bch){+free_bch(info->bch);+info->bch=NULL;}--pr_info("enabling NAND BCH ecc with %d-bit correction\n",max_errors);-return0;-fail:-omap3_free_bch(mtd);-return-1;}/**
@@ -1806,11 +1741,6 @@ fail:}#else-staticintomap3_init_bch(structmtd_info*mtd,intecc_opt)-{-pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");-return-1;-}staticintomap3_init_bch_tail(structmtd_info*mtd){return-1;
@@ -1851,15 +1781,14 @@ static int omap_nand_probe(struct platform_device *pdev)info->pdev=pdev;info->gpmc_cs=pdata->cs;info->reg=pdata->reg;+info->bch=NULL;+info->of_node=pdata->of_node;mtd=&info->mtd;mtd->priv=&info->nand;mtd->name=dev_name(&pdev->dev);mtd->owner=THIS_MODULE;nand_chip=&info->nand;nand_chip->options|=NAND_SKIP_BBTSCAN;-#ifdef CONFIG_MTD_NAND_OMAP_BCH-info->of_node=pdata->of_node;-#endifres=platform_get_resource(pdev,IORESOURCE_MEM,0);if(res==NULL){
@@ -2001,22 +1930,125 @@ static int omap_nand_probe(struct platform_device *pdev)gotoout_release_mem_region;}-/* select the ecc type */-if(pdata->ecc_opt==OMAP_ECC_HAM1_CODE_HW){+/* populate MTD interface based on ECC scheme */+switch(pdata->ecc_opt){+caseOMAP_ECC_HAM1_CODE_HW:+pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");+nand_chip->ecc.mode=NAND_ECC_HW;nand_chip->ecc.bytes=3;nand_chip->ecc.size=512;nand_chip->ecc.strength=1;nand_chip->ecc.calculate=omap_calculate_ecc;nand_chip->ecc.hwctl=omap_enable_hwecc;nand_chip->ecc.correct=omap_correct_data;-nand_chip->ecc.mode=NAND_ECC_HW;-}elseif((pdata->ecc_opt==OMAP_ECC_BCH4_CODE_HW)||-(pdata->ecc_opt==OMAP_ECC_BCH8_CODE_HW)){-err=omap3_init_bch(mtd,pdata->ecc_opt);-if(err){+break;++caseOMAP_ECC_BCH4_CODE_HW_DETECTION_SW:+#ifdef CONFIG_MTD_NAND_ECC_BCH+pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");+nand_chip->ecc.mode=NAND_ECC_HW;+nand_chip->ecc.size=512;+nand_chip->ecc.bytes=7;+nand_chip->ecc.strength=4;+nand_chip->ecc.hwctl=omap3_enable_hwecc_bch;+nand_chip->ecc.correct=omap3_correct_data_bch;+nand_chip->ecc.calculate=omap3_calculate_ecc_bch4;+/* software bch library is used for locating errors */+info->bch=init_bch(nand_chip->ecc.bytes,+nand_chip->ecc.strength,+OMAP_ECC_BCH8_POLYNOMIAL);+if(!info->bch){+pr_err("nand: error: unable to use s/w BCH library\n");err=-EINVAL;+}+break;+#else+pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");+err=-EINVAL;+gotoout_release_mem_region;+#endif++caseOMAP_ECC_BCH4_CODE_HW:+#ifdef CONFIG_MTD_NAND_OMAP_BCH+pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");+nand_chip->ecc.mode=NAND_ECC_HW;+nand_chip->ecc.size=512;+/* 14th bit is kept reserved for ROM-code compatibility */+nand_chip->ecc.bytes=7+1;+nand_chip->ecc.strength=4;+nand_chip->ecc.hwctl=omap3_enable_hwecc_bch;+nand_chip->ecc.correct=omap_elm_correct_data;+nand_chip->ecc.calculate=omap3_calculate_ecc_bch;+nand_chip->ecc.read_page=omap_read_page_bch;+nand_chip->ecc.write_page=omap_write_page_bch;+/* This ECC scheme requires ELM H/W block */+if(is_elm_present(info,pdata->elm_of_node,BCH4_ECC)<0){+pr_err("nand: error: could not initialize ELM\n");+err=-ENODEV;gotoout_release_mem_region;}+break;+#else+pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");+err=-EINVAL;+gotoout_release_mem_region;+#endif++caseOMAP_ECC_BCH8_CODE_HW_DETECTION_SW:+#ifdef CONFIG_MTD_NAND_ECC_BCH+pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");+nand_chip->ecc.mode=NAND_ECC_HW;+nand_chip->ecc.size=512;+nand_chip->ecc.bytes=13;+nand_chip->ecc.strength=8;+nand_chip->ecc.hwctl=omap3_enable_hwecc_bch;+nand_chip->ecc.correct=omap3_correct_data_bch;+nand_chip->ecc.calculate=omap3_calculate_ecc_bch8;+/* software bch library is used for locating errors */+info->bch=init_bch(nand_chip->ecc.bytes,+nand_chip->ecc.strength,+OMAP_ECC_BCH8_POLYNOMIAL);+if(!info->bch){+pr_err("nand: error: unable to use s/w BCH library\n");+err=-EINVAL;+gotoout_release_mem_region;+}+break;+#else+pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");+err=-EINVAL;+gotoout_release_mem_region;+#endif++caseOMAP_ECC_BCH8_CODE_HW:+#ifdef CONFIG_MTD_NAND_OMAP_BCH+pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");+nand_chip->ecc.mode=NAND_ECC_HW;+nand_chip->ecc.size=512;+/* 14th bit is kept reserved for ROM-code compatibility */+nand_chip->ecc.bytes=13+1;+nand_chip->ecc.strength=8;+nand_chip->ecc.hwctl=omap3_enable_hwecc_bch;+nand_chip->ecc.correct=omap_elm_correct_data;+nand_chip->ecc.calculate=omap3_calculate_ecc_bch;+nand_chip->ecc.read_page=omap_read_page_bch;+nand_chip->ecc.write_page=omap_write_page_bch;+/* This ECC scheme requires ELM H/W block */+if(is_elm_present(info,pdata->elm_of_node,BCH8_ECC)<0){+pr_err("nand: error: could not initialize ELM\n");+gotoout_release_mem_region;+}+break;+#else+pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");+err=-EINVAL;+gotoout_release_mem_region;+#endif++default:+pr_err("nand: error: invalid or unsupported ECC scheme\n");+err=-EINVAL;+gotoout_release_mem_region;}/* rom code layout */
@@ -2038,6 +2070,8 @@ static int omap_nand_probe(struct platform_device *pdev)nand_chip->ecc.layout=&omap_oobinfo;}elseif((pdata->ecc_opt==OMAP_ECC_BCH4_CODE_HW)||+(pdata->ecc_opt==OMAP_ECC_BCH4_CODE_HW_DETECTION_SW)||+(pdata->ecc_opt==OMAP_ECC_BCH8_CODE_HW_DETECTION_SW)||(pdata->ecc_opt==OMAP_ECC_BCH8_CODE_HW)){/* build OOB layout for BCH ECC correction */err=omap3_init_bch_tail(mtd);
generic frame-work in mtd/nand/nand_bch.c is a wrapper above lib/bch.h which
encapsulates all control information specific to BCH ecc algorithm in software.
Thus this patch:
(1) replace omap specific implementations with equivalent wrapper in nand_bch.c
so that generic code from nand_bch.c is re-used. like;
omap3_correct_data_bch() -> nand_bch_correct_data()
omap3_free_bch() -> nand_bch_free()
(2) replace direct calls to lib/bch.c with wrapper functions defined in nand_bch.c
init_bch() -> nand_bch_init()
Signed-off-by: Pekon Gupta <redacted>
---
drivers/mtd/nand/omap2.c | 96 +++++++++++-------------------------------------
1 file changed, 22 insertions(+), 74 deletions(-)
@@ -1913,10 +1853,11 @@ static int omap_nand_probe(struct platform_device *pdev)ecclayout->oobfree->offset=ecclayout->eccpos[0]+ecclayout->eccbytes;/* software bch library is used for locating errors */-info->bch=init_bch(nand_chip->ecc.bytes,-nand_chip->ecc.strength,-OMAP_ECC_BCH8_POLYNOMIAL);-if(!info->bch){+nand_chip->ecc.priv=nand_bch_init(mtd,+nand_chip->ecc.size,+nand_chip->ecc.bytes,+&nand_chip->ecc.layout);+if(!nand_chip->ecc.priv){pr_err("nand: error: unable to use s/w BCH library\n");err=-EINVAL;}
@@ -1978,10 +1919,11 @@ static int omap_nand_probe(struct platform_device *pdev)ecclayout->oobfree->offset=ecclayout->eccpos[0]+ecclayout->eccbytes;/* software bch library is used for locating errors */-info->bch=init_bch(nand_chip->ecc.bytes,-nand_chip->ecc.strength,-OMAP_ECC_BCH8_POLYNOMIAL);-if(!info->bch){+nand_chip->ecc.priv=nand_bch_init(mtd,+nand_chip->ecc.size,+nand_chip->ecc.bytes,+&nand_chip->ecc.layout);+if(!nand_chip->ecc.priv){pr_err("nand: error: unable to use s/w BCH library\n");err=-EINVAL;gotoout_release_mem_region;
"Managed Device Resource" or devm_xx calls takes care of automatic freeing
of the resource in case of:
- failure during driver probe
- failure during resource allocation
- detaching or unloading of driver module (rmmod)
Reference: Documentation/driver-model/devres.txt
Though OMAP NAND driver handles freeing of resource allocation in most of
the cases, but using devm_xx provides more clean and effortless approach
to handle all such cases.
- simplifies label for exiting probe during error
s/out_release_mem_region/return_error
Signed-off-by: Pekon Gupta <redacted>
---
drivers/mtd/nand/omap2.c | 85 ++++++++++++++++++++----------------------------
1 file changed, 35 insertions(+), 50 deletions(-)
@@ -1710,14 +1712,14 @@ static int omap_nand_probe(struct platform_device *pdev)if(nand_scan_ident(mtd,1,NULL)){pr_err("nand device scan failed, may be bus-width mismatch\n");err=-ENXIO;-gotoout_release_mem_region;+gotoreturn_error;}/* check for small page devices */if((mtd->oobsize<64)&&(pdata->ecc_opt!=OMAP_ECC_HAM1_CODE_HW)){pr_err("small page devices are not supported\n");err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;}/* re-populate low-level callbacks based on xfer modes */
@@ -1807,7 +1811,7 @@ static int omap_nand_probe(struct platform_device *pdev)dev_err(&pdev->dev,"xfer_type(%d) not supported!\n",pdata->xfer_type);err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;}/* populate MTD interface based on ECC scheme */
@@ -1865,7 +1869,7 @@ static int omap_nand_probe(struct platform_device *pdev)#elsepr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;#endifcaseOMAP_ECC_BCH4_CODE_HW:
@@ -1892,13 +1896,13 @@ static int omap_nand_probe(struct platform_device *pdev)if(is_elm_present(info,pdata->elm_of_node,BCH4_ECC)<0){pr_err("nand: error: could not initialize ELM\n");err=-ENODEV;-gotoout_release_mem_region;+gotoreturn_error;}break;#elsepr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;#endifcaseOMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
@@ -1926,13 +1930,13 @@ static int omap_nand_probe(struct platform_device *pdev)if(!nand_chip->ecc.priv){pr_err("nand: error: unable to use s/w BCH library\n");err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;}break;#elsepr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;#endifcaseOMAP_ECC_BCH8_CODE_HW:
@@ -1951,7 +1955,7 @@ static int omap_nand_probe(struct platform_device *pdev)/* This ECC scheme requires ELM H/W block */if(is_elm_present(info,pdata->elm_of_node,BCH8_ECC)<0){pr_err("nand: error: could not initialize ELM\n");-gotoout_release_mem_region;+gotoreturn_error;}/* define ECC layout */ecclayout->eccbytes=nand_chip->ecc.bytes*
@@ -1964,13 +1968,13 @@ static int omap_nand_probe(struct platform_device *pdev)#elsepr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;#endifdefault:pr_err("nand: error: invalid or unsupported ECC scheme\n");err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;}/* populate remaining ECC layout data */
@@ -1983,13 +1987,13 @@ static int omap_nand_probe(struct platform_device *pdev)pr_err("not enough OOB bytes required = %d, available=%d\n",ecclayout->eccbytes,mtd->oobsize);err=-EINVAL;-gotoout_release_mem_region;+gotoreturn_error;}/* second phase scan */if(nand_scan_tail(mtd)){err=-ENXIO;-gotoout_release_mem_region;+gotoreturn_error;}ppdata.of_node=pdata->of_node;
@@ -2000,21 +2004,13 @@ static int omap_nand_probe(struct platform_device *pdev)return0;-out_release_mem_region:+return_error:if(info->dma)dma_release_channel(info->dma);-if(info->gpmc_irq_count>0)-free_irq(info->gpmc_irq_count,info);-if(info->gpmc_irq_fifo>0)-free_irq(info->gpmc_irq_fifo,info);-release_mem_region(info->phys_base,info->mem_size);-out_free_info:if(nand_chip->ecc.priv){nand_bch_free(nand_chip->ecc.priv);nand_chip->ecc.priv=NULL;}-kfree(info);-returnerr;}
@@ -2028,20 +2024,9 @@ static int omap_nand_remove(struct platform_device *pdev)nand_bch_free(nand_chip->ecc.priv);nand_chip->ecc.priv=NULL;}-if(info->dma)dma_release_channel(info->dma);--if(info->gpmc_irq_count>0)-free_irq(info->gpmc_irq_count,info);-if(info->gpmc_irq_fifo>0)-free_irq(info->gpmc_irq_fifo,info);--/* Release NAND device, its internal structures and partitions */nand_release(mtd);-iounmap(nand_chip->IO_ADDR_R);-release_mem_region(info->phys_base,info->mem_size);-kfree(info);return0;}
Hi Pekon,
Just as suggestion, I think you should reconsider your 'upstream strategy'.
On Thu, Oct 24, 2013 at 06:20:16PM +0530, Pekon Gupta wrote:
[..]
Pekon Gupta (10):
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes
mtd: nand: omap: cleanup: replace local references with generic framework names
IMHO, this patch about the dobule nand_scan_ident():
mtd: nand: omap: use DT specified bus-width only for scanning NAND device
is a fix unrelated to this series and can be pushed independently.
Maybe you can try to send it as a one-patch fix?
mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe
mtd: nand: omap: clean-up ecc layout for BCH ecc schemes
mtd: nand: omap: use drivers/mtd/nand/nand_bch.c wrapper for BCH ECC instead of lib/bch.c
ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
And also this patch:
mtd: nand: omap: updated devm_xx for all resource allocation and free calls
doesn't seem to belong to this series.
I think tou could send those two independently and ask Brian to merge them earlier
if appropriate.
But again, this is just a suggestion.
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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@@ -1856,7 +1856,6 @@ static int omap_nand_probe(struct platform_device *pdev)mtd->name=dev_name(&pdev->dev);mtd->owner=THIS_MODULE;nand_chip=&info->nand;-nand_chip->options=pdata->devsize;nand_chip->options|=NAND_SKIP_BBTSCAN;#ifdef CONFIG_MTD_NAND_OMAP_BCHinfo->of_node=pdata->of_node;
@@ -1904,6 +1903,15 @@ static int omap_nand_probe(struct platform_device *pdev)nand_chip->chip_delay=50;}+/* scan NAND device connected to chip controller */+nand_chip->options|=pdata->devsize&NAND_BUSWIDTH_16;
Hm.. this only works if the device is listed in nand_flash_ids[] array,
so that ONFI detection is not used. To make ONFI detection work I think you
need to do as Brian suggested and use NAND_BUSWIDTH_AUTO.
(Odd: why is there no current user of that auto-width option?)
Anyway, I really think we should fix this now and independently
of the evolution of this ECC DT binding discussion.
That way you can keep sending a smaller ECC DT binding patchset and
make reviewers focus on what's really important in each case.
I have a few fixes (based on your work) and I'll send them now, after
I complete the tests. We can continue our discussion there.
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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@@ -1856,7 +1856,6 @@ static int omap_nand_probe(struct platform_device *pdev)mtd->name=dev_name(&pdev->dev);mtd->owner=THIS_MODULE;nand_chip=&info->nand;-nand_chip->options=pdata->devsize;nand_chip->options|=NAND_SKIP_BBTSCAN;#ifdef CONFIG_MTD_NAND_OMAP_BCHinfo->of_node=pdata->of_node;
@@ -1904,6 +1903,15 @@ static int omap_nand_probe(struct platform_device *pdev)nand_chip->chip_delay=50;}+/* scan NAND device connected to chip controller */+nand_chip->options|=pdata->devsize&NAND_BUSWIDTH_16;
Hm.. this only works if the device is listed in nand_flash_ids[] array,
so that ONFI detection is not used.
But this is no more broken than it used to be, no? I mean, you would
never properly detect an x16 ONFI flash with the old
double-nand_scan_ident() method, right?
To make ONFI detection work I think you
need to do as Brian suggested and use NAND_BUSWIDTH_AUTO.
I think that is the correct way forward. But Pekon seems to think that
will require more invasive changes to the GPMC code. But I'm not sure
why.
(Odd: why is there no current user of that auto-width option?)
Hmm, I could have sworn somebody was using that... I know there was some
pending work on using it for GPIO NAND, but Alexander Shiyan never
followed up on the latest comments. It also seems like the original
author (Matthieu Castet) was working on OMAP support about a year ago,
but things stalled when there wasn't proper mainline support for much of
it:
http://thread.gmane.org/gmane.linux.ports.arm.omap/88550/focus=44770
Personally, I've only ever used x8 NAND, so I don't have much to go on
here.
Anyway, I really think we should fix this now and independently
of the evolution of this ECC DT binding discussion.
That way you can keep sending a smaller ECC DT binding patchset and
make reviewers focus on what's really important in each case.
AFAIK, the ECC DT bindings were all approved, and the code looked OK to
my knowledge, except for this single patch. I had recommended either its
total removal or its simplification (i.e., this current patch).
I will be taking a last look and queueing this series up soon, I
believe.
I have a few fixes (based on your work) and I'll send them now, after
I complete the tests. We can continue our discussion there.
I'll take a look at those soon.
So am I to understand you have hardware for testing Pekon's work now,
Ezequiel? That will be great if we can have better Reviewed-by/Tested-by
results.
Brian
@@ -1856,7 +1856,6 @@ static int omap_nand_probe(struct platform_device *pdev)mtd->name=dev_name(&pdev->dev);mtd->owner=THIS_MODULE;nand_chip=&info->nand;-nand_chip->options=pdata->devsize;nand_chip->options|=NAND_SKIP_BBTSCAN;#ifdef CONFIG_MTD_NAND_OMAP_BCHinfo->of_node=pdata->of_node;
@@ -1904,6 +1903,15 @@ static int omap_nand_probe(struct platform_device *pdev)nand_chip->chip_delay=50;}+/* scan NAND device connected to chip controller */+nand_chip->options|=pdata->devsize&NAND_BUSWIDTH_16;
Hm.. this only works if the device is listed in nand_flash_ids[] array,
so that ONFI detection is not used.
But this is no more broken than it used to be, no? I mean, you would
never properly detect an x16 ONFI flash with the old
double-nand_scan_ident() method, right?
That's right. But the issue is not really fixed either.
quoted
To make ONFI detection work I think you
need to do as Brian suggested and use NAND_BUSWIDTH_AUTO.
I think that is the correct way forward. But Pekon seems to think that
will require more invasive changes to the GPMC code. But I'm not sure
why.
Hm... not sure. AFAIK, the GPMC should be *already* configured prior to the
NAND driver being probed.
quoted
(Odd: why is there no current user of that auto-width option?)
Hmm, I could have sworn somebody was using that... I know there was some
pending work on using it for GPIO NAND, but Alexander Shiyan never
followed up on the latest comments. It also seems like the original
author (Matthieu Castet) was working on OMAP support about a year ago,
but things stalled when there wasn't proper mainline support for much of
it:
http://thread.gmane.org/gmane.linux.ports.arm.omap/88550/focus=44770
Personally, I've only ever used x8 NAND, so I don't have much to go on
here.
quoted
Anyway, I really think we should fix this now and independently
of the evolution of this ECC DT binding discussion.
That way you can keep sending a smaller ECC DT binding patchset and
make reviewers focus on what's really important in each case.
AFAIK, the ECC DT bindings were all approved, and the code looked OK to
my knowledge, except for this single patch. I had recommended either its
total removal or its simplification (i.e., this current patch).
FWIW, I'm in favor of *completely* dropping whatever doesn't belong
to the ECC DT binding.
I will be taking a last look and queueing this series up soon, I
believe.
quoted
I have a few fixes (based on your work) and I'll send them now, after
I complete the tests. We can continue our discussion there.
I'll take a look at those soon.
Ok, cool.
So am I to understand you have hardware for testing Pekon's work now,
Ezequiel? That will be great if we can have better Reviewed-by/Tested-by
results.
Yup, I gave it quick test actually, but nothing deep. Let me test some
more maybe later today/tomorrow. I just wanted to sort this out first.
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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Pekon,
On Thu, Oct 24, 2013 at 06:20:16PM +0530, Pekon Gupta wrote:
*changes v10 -> v11*
- [PATCH v10 04/10] replaced with newer [PATCH v11 04/11] so that
nand_scan_ident() is called only once.
discussion thread with Brian Norris [off-list ref]
<http://lists.infradead.org/pipermail/linux-mtd/2013-October/049335.html>
- No change in any other patch
*changes v9 -> v10*
[PATCH 1/10], [PATCH 2/10]
swapped [PATCH v9 1/9] and [PATCH v9 2/9] so that DT parsing updates
(with backward compatibility) happen before the deprecation of DT values.
This way DTB does not break functionally between the patches.
[PATCH 3/10] <no update>
[PATCH 4/10]
dropped [PATCH v9 4/9] introducing NAND_BUSWIDTH_AUTO, instead
using DT 'nand-bus-width' for device bus-width. Refer discussion thread
<http://lists.infradead.org/pipermail/linux-mtd/2013-October/049198.html>
[PATCH 5/10] <no update>
[PATCH 6/10] <no update>
[PATCH 7/10]
separated out drivers/mtd/nand/Kconfig updates into separate [PATCH v10 10/10]
cleanup: s/info->nand\./nand_chip->
[PATCH 8/10] <no update>
[PATCH 9/10] cleanup: s/out_release_mem_region/return_error
[PATCH 10/10] <new> spawned from [PATCH v9 8/9] for Kconfig updates
*changes v8 -> v9*
[PATCH 1/9] <no update from [PATCH v8 1/6]>
[PATCH 2/9] <only commit log updated from [PATCH v8 2/6]>
As per feedbacks from Brian Norris [off-list ref] previous
revision [PATCH v8 3/6] and [PATCH 4/6] are split into following sub-patches:
- [PATCH 3/9] <new> replaces local reference with generic names (mtd, nand_chip)
- [PATCH 4/9] <new> enables auto-detection of bus-width
- [PATCH 5/9] <new> removes omap3_init_bch: populates ecc-scheme data
- [PATCH 6/9] <new> removes omap3_init_bch_tail: populates ecc-layout
- [PATCH 7/9] <new> replaces lib/bch.c with nand_bch.c wrapper
[PATCH 8/9] <no update same as [PATCH v8 5/6]
[PATCH 9/9] removed devm_free_xx functions
*Changes v7 -> v8*
[PATCH 1/6] <no updates>
[PATCH 2/6]
- updated DT parsing of "ti,nand-ecc-opts" so that its "ham1" remains
compatible to "sw","hw","hw-romcode"
- updated DT parsing of "ti,elm-id" to retain compatibility to "elm_id"
- using of_parse_phandle() to get ELM device pointer from DT
[PATCH 3..6/6] <commit log updates>
*Changes v6 -> v7*
[PATCH 1/6] <NEW> split from [PATCH v6 2/4] as per feedbacks from Brian Norris [off-list ref]
[PATCH 2/6] incorporated feedbacks from DT maintainers
[PATCH 3/6] cleaned and incorporated feedbacks from Brian Norris [off-list ref]
[PATCH 4/6] rebasing changes and cleanup
[PATCH 5/6] updated omap3430-sdp.dts
[PATCH 6/6] <NEW> updated for devm_xx
*Changes v5 -> v6*
[PATCH 1/4]:
- updated DT binding for gpmc-nand based on 'Olof Johansson's feedbacks
http://lists.infradead.org/pipermail/linux-mtd/2013-August/048394.html
- detection of ELM device via ti,elm-id DT node, moved to gpmc.c driver
[PATCH 2/4]
- removed: support for following obselete ECC schemes
OMAP_ECC_HAMMING_CODE_DEFAULT (S/W based 1-bit Hamming ECC)
OMAP_ECC_HAMMING_CODE_HW_ROMCODE (H/W based 1-bit Hamming ECC scheme)
- updated: using omap_oobinfo as chip->ecc.layout for all ecc-schemes
- clean: error messages
[PATCH 3/4] cleaned to include changes for OMAP_ECC_BCH8_CODE_HW only
[PATCH 4/4] updated to include DT property changes
*Changes v4 -> v5*
- Rebased to linux-next
IMPORTANT: Need to revert commit fb1585b, [PATCH 2/4] part of previous version
http://lists.infradead.org/pipermail/linux-mtd/2013-July/047441.html
- Swapped PATCH-1 & PATCH-2 to maintain bisectibility & compilation dependency
http://lists.infradead.org/pipermail/linux-mtd/2013-July/047461.html
- PATCH-2: re-ordered call to is_elm_present() for later updates ELM driver
- dropped changes in include/linux/platform_data/elm.h (not needed)
- PATCH-3: re-ordered call to is_elm_present() for later updates ELM driver
- Re-formated patch description (replaced tabs with white-spaces)
*Changes v3 -> v4*
(Resent with CC: devicetree-discuss@lists.ozlabs.org)
- [Patch 1/3] removed MTD_NAND_OMAP_BCH8 & MTD_NAND_OMAP_BCH4 from nand/Kconfig
ECC scheme selectable via nand DT (nand-ecc-opt).
- [*] rebased for l2-mtd.git
*Changes v2 -> v3*
(Resent with Author Name fixed)
- PATCH-1: re-arranged code to remove redundancy, added NAND_BUSWIDTH_AUTO
- PATCH-2: updated nand-ecc-opt DT mapping and Documentation
- PATCH-3: code-cleaning + changes to match PATCH-1
- PATCH-4 <DROPPED> update DT attribute for ti,nand-ecc-opt
- received feedback to keep DT mapping independent of linuxism
- PATCH-4:<NEW> : ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
- independent patch for AM335x-evm.dts update based on PATCH-2
*Changes v1 -> v2*
added [PATCH 3/4] and [PATCH 4/4]
After this patch series, omap2-nand driver will supports following ECC schemes:
+---------------------------------------+---------------+---------------+
| ECC scheme |ECC calculation|Error detection|
+---------------------------------------+---------------+---------------+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id) | | |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id) | | |
+---------------------------------------+---------------+---------------+
Pekon Gupta (10):
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
mtd: nand: omap: combine different flavours of 1-bit hamming ecc
schemes
mtd: nand: omap: cleanup: replace local references with generic
framework names
mtd: nand: omap: use DT specified bus-width only for scanning NAND
device
mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in
device_probe
mtd: nand: omap: clean-up ecc layout for BCH ecc schemes
mtd: nand: omap: use drivers/mtd/nand/nand_bch.c wrapper for BCH ECC
instead of lib/bch.c
ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
mtd: nand: omap: updated devm_xx for all resource allocation and free
calls
mtd: nand: omap: remove selection of BCH ecc-scheme via KConfig
.../devicetree/bindings/mtd/gpmc-nand.txt | 16 +-
arch/arm/boot/dts/am335x-evm.dts | 3 +-
arch/arm/boot/dts/omap3430-sdp.dts | 2 +-
arch/arm/mach-omap2/board-flash.c | 2 +-
arch/arm/mach-omap2/gpmc.c | 48 +-
drivers/mtd/nand/Kconfig | 40 +-
drivers/mtd/nand/omap2.c | 641 +++++++++------------
include/linux/platform_data/mtd-nand-omap2.h | 18 +-
8 files changed, 348 insertions(+), 422 deletions(-)
I tested this using the AM335x device tree you posted earlier with
the 16-bit NAND Beaglebone cape. For all the patches:
Tested-by: Ezequiel Garcia <redacted>
The ECC bindings look much much cleaner now, nice job!
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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From: Brian Norris <computersforpeace@gmail.com> Date: 2013-10-30 03:59:57
On Thu, Oct 24, 2013 at 9:52 AM, Ezequiel Garcia
[off-list ref] wrote:
Just as suggestion, I think you should reconsider your 'upstream strategy'.
On Thu, Oct 24, 2013 at 06:20:16PM +0530, Pekon Gupta wrote:
[..]
quoted
Pekon Gupta (10):
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes
mtd: nand: omap: cleanup: replace local references with generic framework names
IMHO, this patch about the dobule nand_scan_ident():
quoted
mtd: nand: omap: use DT specified bus-width only for scanning NAND device
is a fix unrelated to this series and can be pushed independently.
Maybe you can try to send it as a one-patch fix?
quoted
mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe
mtd: nand: omap: clean-up ecc layout for BCH ecc schemes
mtd: nand: omap: use drivers/mtd/nand/nand_bch.c wrapper for BCH ECC instead of lib/bch.c
ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
And also this patch:
quoted
mtd: nand: omap: updated devm_xx for all resource allocation and free calls
doesn't seem to belong to this series.
I think tou could send those two independently and ask Brian to merge them earlier
if appropriate.
But again, this is just a suggestion.
I agree with Ezequiel's thoughts, since the excessive amount of noise
in this patch series has delayed it significantly. But at this point,
I think it has stabilized; we have reviews from the DT folks (thanks
guys; please comment if you have an official "ack" to give), and I
think we've retained backwards compatibility properly; I've combed
through it a few times over the months; we have a third-party tester;
and at this point, I'm sure we're all sick of this.
So, without further delay: pushed all patches except path 8 to l2-mtd.git.
Tony, you mentioned the DTS update in patch 8 going in via an ARM
tree? This patch is not urgent, and it should probably wait until we
know what release the rest of the series makes it into. This may
depend on David Woodhouse's recommendation, but I'm not sure this
series will have enough time baking in linux-next before entering
mainline in 3.13 (the merge window is approaching).
Pekon/Ezequiel/others: please feel free to send any follow up cleanups
for this driver. I'll take a look at what Ezequiel has already sent
out and see if it's still applicable on top.
Thanks,
Brian
On Tue, Oct 29, 2013 at 11:59:57PM -0400, Brian Norris wrote:
Pekon/Ezequiel/others: please feel free to send any follow up cleanups
for this driver. I'll take a look at what Ezequiel has already sent
out and see if it's still applicable on top.
They won't. I'll prepare a new patch in top of latest l2-mtd.
It's good to see this DT discussion finally coming to an end! Good job!
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
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From: Brian Norris [mailto:computersforpeace@gmail.com]
[...]
I agree with Ezequiel's thoughts, since the excessive amount of noise
in this patch series has delayed it significantly. But at this point,
I think it has stabilized; we have reviews from the DT folks (thanks
guys; please comment if you have an official "ack" to give), and I
think we've retained backwards compatibility properly; I've combed
through it a few times over the months; we have a third-party tester;
and at this point, I'm sure we're all sick of this.
So, without further delay: pushed all patches except path 8 to l2-mtd.git.
Thanks much ..
I'll ensure that my next series are more logically aligned.
Tony, you mentioned the DTS update in patch 8 going in via an ARM
tree? This patch is not urgent, and it should probably wait until we
know what release the rest of the series makes it into. This may
depend on David Woodhouse's recommendation, but I'm not sure this
series will have enough time baking in linux-next before entering
mainline in 3.13 (the merge window is approaching).
Pekon/Ezequiel/others: please feel free to send any follow up cleanups
for this driver. I'll take a look at what Ezequiel has already sent
out and see if it's still applicable on top.
Yes, I have other pending series, which I'll resend after rebasing on
this v11. But those are limited to internal NAND driver clean-up only
And do not touch DT or any other dependent driver.
with regards, pekon
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
From: Tony Lindgren <tony@atomide.com> Date: 2013-10-31 21:23:49
* Brian Norris [off-list ref] [131029 21:00]:
Tony, you mentioned the DTS update in patch 8 going in via an ARM
tree? This patch is not urgent, and it should probably wait until we
know what release the rest of the series makes it into. This may
depend on David Woodhouse's recommendation, but I'm not sure this
series will have enough time baking in linux-next before entering
mainline in 3.13 (the merge window is approaching).
Yes Benoit or I can apply that patch if Pekon pings me or resends
that patch when it's OK to merge it.
Regards,
Tony
* Brian Norris [off-list ref] [131029 21:00]:
Tony, you mentioned the DTS update in patch 8 going in via an ARM
tree? This patch is not urgent, and it should probably wait until we
know what release the rest of the series makes it into. This may
depend on David Woodhouse's recommendation, but I'm not sure this
series will have enough time baking in linux-next before entering
mainline in 3.13 (the merge window is approaching).
Yes Benoit or I can apply that patch if Pekon pings me or resends
that patch when it's OK to merge it.
Yes, I'll keep track of this and would resend you and Benoit the .dts patch
separately when this these binding updates are merged in kernel.
with regards, pekon