--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c

@@ -420,6 +420,29 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
 	return 0;
 }
 
+static void _set_gpio_mode(struct gpio_bank *bank, unsigned offset)
+{
+	if (bank->regs->pinctrl) {
+		void __iomem *reg = bank->base + bank->regs->pinctrl;
+
+		/* Claim the pin for MPU */
+		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
+	}
+
+	if (bank->regs->ctrl && !bank->mod_usage) {
+		void __iomem *reg = bank->base + bank->regs->ctrl;
+		u32 ctrl;
+
+		ctrl = __raw_readl(reg);
+		/* Module is enabled, clocks are not gated */
+		ctrl &= ~GPIO_MOD_CTRL_BIT;
+		__raw_writel(ctrl, reg);
+		bank->context.ctrl = ctrl;
+	}
+
+	bank->mod_usage |= 1 << offset;
+}
+
 static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);

@@ -427,8 +450,8 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
 	int retval;
 	unsigned long flags;
 
-	if (WARN_ON(!bank->mod_usage))
-		return -EINVAL;
+	if (!bank->mod_usage)
+		pm_runtime_get_sync(bank->dev);
 
 #ifdef CONFIG_ARCH_OMAP1
 	if (d->irq > IH_MPUIO_BASE)

@@ -438,6 +461,11 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
 	if (!gpio)
 		gpio = irq_to_gpio(bank, d->hwirq);
 
+	spin_lock_irqsave(&bank->lock, flags);
+	_set_gpio_mode(bank, GPIO_INDEX(bank, gpio));
+	_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
+	spin_unlock_irqrestore(&bank->lock, flags);
+
 	if (type & ~IRQ_TYPE_SENSE_MASK)
 		return -EINVAL;