Hi Thierry,

Subject: Re: [PATCH 4/4] Documentation: Add device tree bindings for
Freescale FTM PWM

On Thu, Aug 22, 2013 at 08:26:10AM +0200, Sascha Hauer wrote:

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On Thu, Aug 22, 2013 at 02:55:42AM +0000, Xiubo Li-B47053 wrote:

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Hi Tomasz,

Thanks for your comments.

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Could you explain meaning of this property more precisely? I'm
interested especially how is this related to the PWM IP block and

boards.

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Yes.
There are 8 channels most. While the pinctrls of 4th and 5th
channels could be used by uart's Rx and Tx, then these 2 channels
won't be used for pwm output, so there will be 6 channels available

by the pwm.

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Thus, the pwm chip will register only 6 pwms(6 channels)
most("fsl,pwm-channel-orders = {0 1 2 3 6 7}").And also the "fsl,pwm-

channel-number" will be 6.

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If the chip has eight PWMs I would register all of them. If some of
them are not routed out by the pinmux then just nothing happens if you
use them. In a sane devicetree they won't be referenced anyway when
they are not routed out of the SoC.

In that case, shouldn't this be hooked up to the pinctrl subsystem as
well? As I understand the above, the logical thing would be for each PWM
channel's .request() operation to configure the pinmuxing appropriately.
And if it can't be configured as necessary then .request() should return
an error (or propagate the error from the pinctrl subsystem).

That's maybe better, if so, the pinctrl configuration must be split into two steps:
1, get the channel pinctrl "active" and "idle" states by callig pinctrl_lookup_state() in .request().
2, select the proper state in .enable()/.disable().




Thanks very much.

--
Best Regards.
Xiubo