On Thu, Aug 16, 2012 at 09:18:20AM -0600, Stephen Warren wrote:

On 08/15/2012 12:49 AM, Thierry Reding wrote:
...

quoted

Stephen: Could you try to find out whether the regular
configuration space translation can just be omitted if we already
set up the one for the extended configuration space? In
tegra_pcie_setup_translations(), BAR 0 is setup for regular
configuration space (which requires a 16 MiB region), while BAR 1
is setup for the extended configuration space (requiring a full 256
MiB region). However, if I understand correctly, each of the
registers that can be accessed via the BAR 0 translation can also
be accessed via the BAR 1 translation. That seems like we're 
wasting the 16 MiB set aside for the BAR 0 mapping.

I have confirmed that in theory, the EXTCFG space can indeed be used
to access any register, making the regular config space redundant.
However, using the HW this way has apparently received less validation.

Okay. I wasn't expecting anything else really. I'll give this a try next
time I get my hands on some Tegra hardware. If that works maybe we
should make up for the missing validation by testing this more
thoroughly.

Thierry