Re: [PATCH 2/2] spi: Add SPI master controller for OCTEON SOCs.
From: David Daney <hidden>
Date: 2012-08-21 19:30:23
Also in:
linux-mips, linux-spi, lkml
On 05/19/2012 10:46 PM, Grant Likely wrote:
On Fri, 11 May 2012 14:34:46 -0700, David Daney [off-list ref] wrote:quoted
From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> Add the driver, link it into the kbuild system and provide device tree binding documentation. Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>Some comments below, but you can add my a-b: Acked-by: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
[...]
quoted
+ p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start, + resource_size(res_mem));Nasty cast. p->register_base needs to be an __iomem pointer variable.
No, it is only ever used as an argument to cvmx_{read,write}_csr(),
which want the u64 type.
The fact taht cvmx_read_csr accepts a uint64_t instead of an __iomem pointer looks really wrong. Why is it written that way?
Register addresses on OCTEON are 64-bits wide. In a 32-bit kernel, pointers are only 32-bits wide. Thus was born the cvmx_read_csr() function that takes a u64 address. We no longer support 32-bit kernels, but the legacy of the interface lives on. David Daney ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/